In this paper, two hardware-controlled update-based cache coherence protocols are presented. The paper discusses the two major disadvantages of the update protocols: inefficiency of updates and the mismatch between the granularity of synchronization and the data transfer. The paper presents two enhancements to the update-based protocols, a write combining scheme and a finer grain synchronization, to overcome these disadvantages. The results demonstrate the effectiveness of these enhancements that, when used together, allow the update-based protocols to significantly improve the execution time of a set of scientific applications when compared to three invalidate-based protocols.

The proceedings of the October 1994 symposium comprise 86 papers in sessions devoted to algorithms (three sessions), applications (three sessions), architecture, communications, distributed algorithms, distributed models, distributed systems (three sessions), fault tolerant systems, interconnection

Fine and medium grain parallelism continues to hold its own as a vital, vibrant research topic. Within the area, new developments in superscalar and VLIW architectures and their associated compilation techniques, have provided exciting new avenues to extract performance from a slowing technology curve.Comprising 28 full-length papers and a number of short (poster) papers, this publication offers a high quality exploration of the current state-of-the art in the field. It will be of particular interest to those involved in control structures and microprogramming; processor architectures; computer system implementation; programming techniques; and software engineering.

Overall, this work demonstrates that update-based protocols can be used not only as a coherence mechanism, but also as a latency reducing and tolerating technique to improve the performance of a set of fine-grain scientific applications. But as with other latency reducing techniques, such as data prefetch, the technique must be used with an understanding of its consequences.

In this paper, we present the details of the two update-based cache coherence protocols for scalable shared-memory multiprocessors that were studied in our previous work. First, the directory structures required for the protocols are briefly reviewed. Next, the state diagrams and some examples of the two update-based protocols are presented; one of the protocols is based on a centralized directory, and the other is based on a singly-linked distributed directory. Protocol deadlock and the additional requirements placed the protocols to avoid such deadlock are also examined. Finally, protocol validation using an exhaustive validation tool known as Murphi is discussed.