This book focuses on foundry-based process technology that enables the fabrication of 3-D ICs. The core of the book discusses the technology platform for pre-packaging wafer lever 3-D ICs. However, this book does not include a detailed discussion of 3-D ICs design and 3-D packaging. This is an edited book based on chapters contributed by various experts in the field of wafer-level 3-D ICs process technology. They are from academia, research labs and industry.

Edited by key figures in 3D integration and written by top authors from high-tech companies and renowned research institutions, this book covers the intricate details of 3D process technology. As such, the main focus is on silicon via formation, bonding and debonding, thinning, via reveal and backside processing, both from a technological and a materials science perspective. The last part of the book is concerned with assessing and enhancing the reliability of the 3D integrated devices, which is a prerequisite for the large-scale implementation of this emerging technology. Invaluable reading for materials scientists, semiconductor physicists, and those working in the semiconductor industry, as well as IT and electrical engineers.

Physical Design for 3D Integrated Circuits reveals how to effectively and optimally design 3D integrated circuits (ICs). It also analyzes the design tools for 3D circuits while exploiting the benefits of 3D technology. The book begins by offering an overview of physical design challenges with respect to conventional 2D circuits, and then each chapter delivers an in-depth look at a specific physical design topic. This comprehensive reference: Contains extensive coverage of the physical design of 2.5D/3D ICs and monolithic 3D ICs Supplies state-of-the-art solutions for challenges unique to 3D circuit design Features contributions from renowned experts in their respective fields Physical Design for 3D Integrated Circuits provides a single, convenient source of cutting-edge information for those pursuing 2.5D/3D technology.

This book explains one of the hottest topics in wireless and electronic devices community, namely the wireless communication at mmWave frequencies, especially at the 60 GHz ISM band. It provides the reader with knowledge and techniques for mmWave antenna design, evaluation, antenna and chip packaging. Addresses practical engineering issues such as RF material evaluation and selection, antenna and packaging requirements, manufacturing tolerances, antenna and system interconnections, and antenna One of the first books to discuss the emerging research and application areas, particularly chip packages with integrated antennas, wafer scale mmWave phased arrays and imaging Contains a good number of case studies to aid understanding Provides the antenna and packaging technologies for the latest and emerging applications with the emphases on antenna integrations for practical applications such as wireless USB, wireless video, phase array, automobile collision avoidance radar, and imaging

The focus behind this book on wafer bonding is the fast paced changes in the research and development in three-dimensional (3D) integration, temporary bonding and micro-electro-mechanical systems (MEMS) with new functional layers. Written by authors and edited by a team from microsystems companies and industry-near research organizations, this handbook and reference presents dependable, first-hand information on bonding technologies. Part I sorts the wafer bonding technologies into four categories: Adhesive and Anodic Bonding; Direct Wafer Bonding; Metal Bonding; and Hybrid Metal/Dielectric Bonding. Part II summarizes the key wafer bonding applications developed recently, that is, 3D integration, MEMS, and temporary bonding, to give readers a taste of the significant applications of wafer bonding technologies. This book is aimed at materials scientists, semiconductor physicists, the semiconductor industry, IT engineers, electrical engineers, and libraries.

This issue of ECS Transactions covers emerging materials, process and technology options for large-area silicon wafers to enhance advanced IC performance or to enable revolutionary device structures with entirely new functionalities. Topics : high-mobility channel materials, (e.g. strained Si/Ge, compound semiconductors and graphene), high-performance gate stacks and low-resistivity junctions and contacts on new, Si-compatible materials; new materials and processes for 3-D (TSV) integration ; synthesis of nano-structures including wires, pores and membranes of Si-compatible materials; novel MEMS/NEMS structures and their integration with the mainstream Si-IC technology.

Three-dimensional (3D) integration is identified as a possible avenue for continuous performance growth in integrated circuits (IC) as the conventional scaling approach is faced with unprecedented challenges in fundamental and economic limits. Wafer level 3D IC can take several forms, and they usually include a stack of several thinned IC layers th