VLSI 2010 Annual Symposium will present extended versions of the best papers presented in ISVLSI 2010 conference. The areas covered by the papers will include among others: Emerging Trends in VLSI, Nanoelectronics, Molecular, Biological and Quantum Computing. MEMS, VLSI Circuits and Systems, Field-programmable and Reconfigurable Systems, System Level Design, System-on-a-Chip Design, Application-Specific Low Power, VLSI System Design, System Issues in Complexity, Low Power, Heat Dissipation, Power Awareness in VLSI Design, Test and Verification, Mixed-Signal Design and Analysis, Electrical/Packaging Co-Design, Physical Design, Intellectual property creating and sharing.

This book provides an overview of current Intellectual Property (IP) based System-on-Chip (SoC) design methodology and highlights how security of IP can be compromised at various stages in the overall SoC design-fabrication-deployment cycle. Readers will gain a comprehensive understanding of the security vulnerabilities of different types of IPs. This book would enable readers to overcome these vulnerabilities through an efficient combination of proactive countermeasures and design-for-security solutions, as well as a wide variety of IP security and trust assessment and validation techniques. This book serves as a single-source of reference for system designers and practitioners for designing secure, reliable and trustworthy SoCs.

This book features research work presented at the 2nd International Conference on Data Engineering and Communication Technology (ICDECT) held on December 15–16, 2017 at Symbiosis International University, Pune, Maharashtra, India. It discusses advanced, multi-disciplinary research into smart computing, information systems and electronic systems, focusing on innovation paradigms in system knowledge, intelligence and sustainability that can be applied to provide feasible solutions to varied problems in society, the environment and industry. It also addresses the deployment of emerging computational and knowledge transfer approaches, optimizing solutions in a variety of disciplines of computer science and electronics engineering.

This book provides a comprehensive coverage of System-on-Chip (SoC) post-silicon validation and debug challenges and state-of-the-art solutions with contributions from SoC designers, academic researchers as well as SoC verification experts. The readers will get a clear understanding of the existing debug infrastructure and how they can be effectively utilized to verify and debug SoCs.

This book explores up-to-date research trends and achievements on low-power and high-speed technologies in both electronics and optics. It offers unique insight into low-power and high-speed approaches ranging from devices, ICs, sub-systems and networks that can be exploited for future mobile devices, 5G networks, Internet of Things (IoT), and data centers. It collects heterogeneous topics in place to catch and predict future research directions of devices, circuits, subsystems, and networks for low-power and higher-speed technologies. Even it handles about artificial intelligence (AI) showing examples how AI technology can be combined with concurrent electronics. Written by top international experts in both industry and academia, the book discusses new devices, such as Si-on-chip laser, interconnections using graphenes, machine learning combined with CMOS technology, progresses of SiGe devices for higher-speed electronices for optic, co-design low-power and high-speed circuits for optical interconnect, low-power network-on-chip (NoC) router, X-ray quantum counting, and a design of low-power power amplifiers. Covers modern high-speed and low-power electronics and photonics. Discusses novel nano-devices, electronics & photonic sub-systems for high-speed and low-power systems, and many other emerging technologies like Si photonic technology, Si-on-chip laser, low-power driver for optic device, and network-on-chip router. Includes practical applications and recent results with respect to emerging low-power systems. Addresses the future perspective of silicon photonics as a low-power interconnections and communication applications.

Given the widespread use of real-time multitasking systems, there are tremendous optimization opportunities if reconfigurable computing can be effectively incorporated while maintaining performance and other design constraints of typical applications. The focus of this book is to describe the dynamic reconfiguration techniques that can be safely used in real-time systems. This book provides comprehensive approaches by considering synergistic effects of computation, communication as well as storage together to significantly improve overall performance, power, energy and temperature.

This book covers various aspects of optimization in design and testing of Network-on-Chip (NoC) based multicore systems. It gives a complete account of the state-of-the-art and emerging techniques for near optimal mapping and test scheduling for NoC-based multicores. The authors describe the use of the Integer Line Programming (ILP) technique for smaller benchmarks and a Particle Swarm Optimization (PSO) to get a near optimal mapping and test schedule for bigger benchmarks. The PSO-based approach is also augmented with several innovative techniques to get the best possible solution. The tradeoff between performance (communication or test time) of the system and thermal-safety is also discussed, based on designer specifications. Provides a single-source reference to design and test for circuit and system-level approaches to (NoC) based multicore systems; Gives a complete account of the state-of-the-art and emerging techniques for near optimal mapping and test scheduling in (NoC) based multicore systems; Organizes chapters systematically and hierarchically, rather than in an ad hoc manner, covering aspects of optimization in design and testing of Network-on-Chip (NoC) based multicore systems.