This book demonstrates the breadth and depth of IP protection through logic locking, considering both attacker/adversary and defender/designer perspectives. The authors draw a semi-chronological picture of the evolution of logic locking during the last decade, gathering and describing all the DO’s and DON’Ts in this approach. They describe simple-to-follow scenarios and guide readers to navigate/identify threat models and design/evaluation flow for further studies. Readers will gain a comprehensive understanding of all fundamentals of logic locking.

A subtle change that leads to disastrous consequences—hardware Trojans undoubtedly pose one of the greatest security threats to the modern age. How to protect hardware against these malicious modifications? One potential solution hides within logic locking; a prominent hardware obfuscation technique. In this book, we take a step-by-step approach to understanding logic locking, from its fundamental mechanics, over the implementation in software, down to an in-depth analysis of security properties in the age of machine learning. This book can be used as a reference for beginners and experts alike who wish to dive into the world of logic locking, thereby having a holistic view of the entire infrastructure required to design, evaluate, and deploy modern locking policies.

With the popularity of hardware security research, several edited monograms have been published, which aim at summarizing the research in a particular field. Typically, each book chapter is a recompilation of one or more research papers, and the focus is on summarizing the state-of-the-art research. Different from the edited monograms, the chapters in this book are not re-compilations of research papers. The book follows a pedagogical approach. Each chapter has been planned to emphasize the fundamental principles behind the logic locking algorithms and relate concepts to each other using a systematization of knowledge approach. Furthermore, the authors of this book have contributed to this field significantly through numerous fundamental papers.

This book is a single-source solution for anyone who is interested in exploring emerging reconfigurable nanotechnology at the circuit level. It lays down a solid foundation for circuits based on this technology having considered both manual as well as automated design flows. The authors discuss the entire design flow, consisting of both logic and physical synthesis for reconfigurable nanotechnology-based circuits. The authors describe how transistor reconfigurable properties can be exploited at the logic level to have a more efficient circuit design flow, as compared to conventional design flows suited for CMOS. Further, the book provides insights into hardware security features that can be intrinsically developed using the runtime reconfigurable features of this nanotechnology.