Based on its ruggedness, solid-state flash memory has been accepted as the basis of code and data storage in embedded systems applications for several decades. In more recent years, widespread mainstream acceptance of flash memory in consumer and enterprise applications has created tremendous downward cost pressures on flash memory manufacturers. The flash memory manufacturers have responded to these pressures by compromising on parameters that are most critical for flash memory's continued suitability for code storage in embedded computer applications. In particular, data retention specifications have been decreased from ten years to as low as one year. This is unacceptable for embedded systems applications that depend on flash memory systems to provide reliable code storage for many years of service. Enabling flash memory systems to continue to reliably support code storage in embedded computer applications requires that wear induced by write requests be minimized. One means of reducing write requests is to reduce the impact of the overhead writes performed by the flash translation layer (FTL) that is used to manage the flash memory while presenting the overall flash memory system as a non-volatile rewritable block device. These overhead write activities may be represented with a measure of Write Amplification Factor (WAF) which is the amount of flash write requests scaled by the amount of write requests performed by the system hosting the flash memory system. In this dissertation, we present FSAware, a novel algorithmic approach that enhances existing FTL designs. Specifically, FSAware reduces overall WAF by separately supporting the write requests associated with the file data and file system overhead produced by host file system write activities. FSAware distinguishes file data write requests from file system overhead write requests by characterizing the file system installed on the flash memory system by the host system. We consider the File Allocation Table (FAT) format, which is specifically selected for its ubiquity in embedded computer applications. FSAware is applicable to both block-mode and page-mode style FTLs. In this work, we develop a novel instrumentation technique called FTLProbe to develop empirical (gray box) models of commercially available drives. Our empirical models are then used to develop WAF equations for file system operations. Simulations of FSAware on commercially available drives are validated with extensions of these WAF equations. Our simulations results show that FSAware can produce a 97% reduction of WAF for a block-mode FTL and a 36% reduction of WAF for a page-mode FTL. Further extension of the WAF equations show that an enhanced FSAware that consolidates meta-data into a single flash allocation unit can theoretically produce a 99% reduction of WAF for a block-mode FTL and a 64% reduction of WAF for a page-mode FTL. With these reductions in overall WAF for file system operations associated with embedded systems, FSAware can form the basis of an ultra-reliable flash memory system for embedded computer applications.

Presented here is an all-inclusive treatment of Flash technology, including Flash memory chips, Flash embedded in logic, binary cell Flash, and multilevel cell Flash. The book begins with a tutorial of elementary concepts to orient readers who are less familiar with the subject. Next, it covers all aspects and variations of Flash technology at a mature engineering level: basic device structures, principles of operation, related process technologies, circuit design, overall design tradeoffs, device testing, reliability, and applications.

Kevin Zhang Advancement of semiconductor technology has driven the rapid growth of very large scale integrated (VLSI) systems for increasingly broad applications, incl- ing high-end and mobile computing, consumer electronics such as 3D gaming, multi-function or smart phone, and various set-top players and ubiquitous sensor and medical devices. To meet the increasing demand for higher performance and lower power consumption in many different system applications, it is often required to have a large amount of on-die or embedded memory to support the need of data bandwidth in a system. The varieties of embedded memory in a given system have alsobecome increasingly more complex, ranging fromstatictodynamic and volatile to nonvolatile. Among embedded memories, six-transistor (6T)-based static random access memory (SRAM) continues to play a pivotal role in nearly all VLSI systems due to its superior speed and full compatibility with logic process technology. But as the technology scaling continues, SRAM design is facing severe challenge in mainta- ing suf?cient cell stability margin under relentless area scaling. Meanwhile, rapid expansion in mobile application, including new emerging application in sensor and medical devices, requires far more aggressive voltage scaling to meet very str- gent power constraint. Many innovative circuit topologies and techniques have been extensively explored in recent years to address these challenges.

NAND flash memory (hereafter, flash memory) has been intensively employed in a wide spectrum of computing systems from mobile devices like smartphones to personal computers to enterprise servers due to its high performance, low power consumption, and shock resistance. However, the further deployment of flash memory is impeded because it also possesses several inherent disadvantages such as limited programming/erase cycles and asymmetrical I/O performance. Besides, the existing frameworks for storage systems are originally designed for block devices (e.g., hard disk drives), which have totally different characteristics from flash memory. In order to utilize flash memory in current storage systems, an extra software layer between a traditional storage system interface and flash memory is needed to mimic the behavior of a block device. Unfortunately, using a flash-based storage system as a traditional HDD noticeably neutralizes the benefits of flash memory.In this dissertation, we holistically examine current flash-based storage systems in different computing platforms ranging from embedded systems to enterprise servers. Firstly, we empirically characterize a representative collection of flash memory devices and then model their raw I/O performance and reliability. Our results demonstrate that flash memory performance and reliability are correlated to programmed data patterns. Further, we propose multiple approaches to improving the performance and reliability of flash-based storage systems at device level. Secondly, we study flash translation layer (FTL) in flash-based solid-state drives (SSDs) for desktops. A plane-centric FTL and a workload-aware MLC/SLC (multi-level cell/single-level cell) partitioning scheme are implemented to boost the performance of a single SSD. Thirdly, the employment of SSD arrays in enterprise servers is investigated. We propose a load-balancing scheme at disk array level to prolong the lifetime of SSD arrays for server applications like OLTP (online transaction processing). Finally, an MTD (memory technology device) array based storage framework will be developed to meet the performance and reliability requirements demanded by emerging and future data-intensive and mission-critical mobile applications.

Embedded computing systems play an important and complex role in the functionality of electronic devices. With our daily routines becoming more reliant on electronics for personal and professional use, the understanding of these computing systems is crucial. Embedded Computing Systems: Applications, Optimization, and Advanced Design brings together theoretical and technical concepts of intelligent embedded control systems and their use in hardware and software architectures. By highlighting formal modeling, execution models, and optimal implementations, this reference source is essential for experts, researchers, and technical supporters in the industry and academia.

This book provides a comprehensive introduction to embedded flash memory, describing the history, current status, and future projections for technology, circuits, and systems applications. The authors describe current main-stream embedded flash technologies from floating-gate 1Tr, floating-gate with split-gate (1.5Tr), and 1Tr/1.5Tr SONOS flash technologies and their successful creation of various applications. Comparisons of these embedded flash technologies and future projections are also provided. The authors demonstrate a variety of embedded applications for auto-motive, smart-IC cards, and low-power, representing the leading-edge technology developments for eFlash. The discussion also includes insights into future prospects of application-driven non-volatile memory technology in the era of smart advanced automotive system, such as ADAS (Advanced Driver Assistance System) and IoE (Internet of Everything). Trials on technology convergence and future prospects of embedded non-volatile memory in the new memory hierarchy are also described. Introduces the history of embedded flash memory technology for micro-controller products and how embedded flash innovations developed; Includes comprehensive and detailed descriptions of current main-stream embedded flash memory technologies, sub-system designs and applications; Explains why embedded flash memory requirements are different from those of stand-alone flash memory and how to achieve specific goals with technology development and circuit designs; Describes a mature and stable floating-gate 1Tr cell technology imported from stand-alone flash memory products - that then introduces embedded-specific split-gate memory cell technologies based on floating-gate storage structure and charge-trapping SONOS technology and their eFlash sub-system designs; Describes automotive and smart-IC card applications requirements and achievements in advanced eFlash beyond 4 0nm node.

This book constitutes the thoroughly refereed post-proceedings of the 9th International Conference on Real-Time and Embedded Systems and Applications, RTCSA 2003, held in Tainan, Taiwan, in February 2003. The 28 revised full papers and 9 revised short papers presented were carefully reviewed and selected for inclusion in the book. The papers are organized in topical sections on scheduling, networking and communication, embedded systems and environments, pervasive and ubiquitous computing, systems and architectures, resource management, file systems and databases, performance analysis, and tools and development.