Designing Asynchronous Circuits using NULL Convention Logic (NCL) begins with an introduction to asynchronous (clockless) logic in general, and then focuses on delay-insensitive asynchronous logic design using the NCL paradigm. The book details design of input-complete and observable dual-rail and quad-rail combinational circuits, and then discusses implementation of sequential circuits, which require datapath feedback. Next, throughput optimization techniques are presented, including pipelining, embedding registration, early completion, and NULL cycle reduction. Subsequently, low-power design techniques, such as wavefront steering and Multi-Threshold CMOS (MTCMOS) for NCL, are discussed. The book culminates with a comprehensive design example of an optimized Greatest Common Divisor circuit. Readers should have prior knowledge of basic logic design concepts, such as Boolean algebra and Karnaugh maps. After studying this book, readers should have a good understanding of the differences between asynchronous and synchronous circuits, and should be able to design arbitrary NCL circuits, optimized for area, throughput, and power. Table of Contents: Introduction to Asynchronous Logic / Overview of NULL Convention Logic (NCL) / Combinational NCL Circuit Design / Sequential NCL Circuit Design / NCL Throughput Optimization / Low-Power NCL Design / Comprehensive NCL Design Example

Unlike conventional synchronous circuits, asynchronous circuits are not coordinated by a clocking signal, but instead use handshaking protocols to control circuit behaviour. Asynchronous circuits have been found to offer several advantages, including high energy efficiency, flexible timing requirements, high modularity, low noise/EMI, and robustness to PVT variations. At the same time, growing pressures on the electronics industry for ever smaller, more efficient ICs are pushing the limits of conventional circuit technologies. These factors are spurring growing interest in asynchronous circuits amongst both the academic research and commercial R&D communities.

Presentation slides from the Devices, Circuits and Systems track at the ETCMOS 2016 conference in Montreal, May 25-27, 2016

Abstracts for presentations at the ETCMOS 2016 conference in Montreal, Canada, May 25 - 27, 2016.

HCTL Open Science and Technology Letters (HCTL Open STL) is an international, open-access, peer-reviewed journal devoted to various disciplines of Science and Technology published (bi-monthly) by HCTL Open Publications Solutions and Hybrid Computing Technology Labs, India. - Get more information at: http://stl.hctl.org/

Research on radiation-tolerant electronics has increased rapidly over the past few years, resulting in many interesting approaches to modeling radiation effects and designing radiation-hardened integrated circuits and embedded systems. This research is strongly driven by the growing need for radiation-hardened electronics for space applications, high-energy physics experiments such as those on the Large Hadron Collider at CERN, and many terrestrial nuclear applications including nuclear energy and nuclear safety. With the progressive scaling of integrated circuit technologies and the growing complexity of electronic systems, their susceptibility to ionizing radiation has raised many exciting challenges, which are expected to drive research in the coming decade. In this book we highlight recent breakthroughs in the study of radiation effects in advanced semiconductor devices, as well as in high-performance analog, mixed signal, RF, and digital integrated circuits. We also focus on advances in embedded radiation hardening in both FPGA and microcontroller systems and apply radiation-hardened embedded systems for cryptography and image processing, targeting space applications.