Three-dimensional (3D) integrated circuit (IC) stacking is the next big step in electronic system integration. It enables packing more functionality, as well as integration of heterogeneous materials, devices, and signals, in the same space (volume). This results in consumer electronics (e.g., mobile, handheld devices) which can run more powerful applications, such as full-length movies and 3D games, with longer battery life. This technology is so promising that it is expected to be a mainstream technology a few years from now, less than 10-15 years from its original conception. To achieve this type of end product, changes in the entire manufacturing and design process of electronic systems are taking place. This book provides readers with an accessible tutorial on a broad range of topics essential to the non-expert in 3D System Integration. It is an invaluable resource for anybody in need of an overview of the 3D manufacturing and design chain.

Three-Dimensional Integrated Circuit Design, Second Eition, expands the original with more than twice as much new content, adding the latest developments in circuit models, temperature considerations, power management, memory issues, and heterogeneous integration. 3-D IC experts Pavlidis, Savidis, and Friedman cover the full product development cycle throughout the book, emphasizing not only physical design, but also algorithms and system-level considerations to increase speed while conserving energy. A handy, comprehensive reference or a practical design guide, this book provides effective solutions to specific challenging problems concerning the design of three-dimensional integrated circuits. Expanded with new chapters and updates throughout based on the latest research in 3-D integration: - Manufacturing techniques for 3-D ICs with TSVs - Electrical modeling and closed-form expressions of through silicon vias - Substrate noise coupling in heterogeneous 3-D ICs - Design of 3-D ICs with inductive links - Synchronization in 3-D ICs - Variation effects on 3-D ICs - Correlation of WID variations for intra-tier buffers and wires - Offers practical guidance on designing 3-D heterogeneous systems - Provides power delivery of 3-D ICs - Demonstrates the use of 3-D ICs within heterogeneous systems that include a variety of materials, devices, processors, GPU-CPU integration, and more - Provides experimental case studies in power delivery, synchronization, and thermal characterization

A. K. TURNER Department of Geology and Geological Engineering Colorado School of Mines Golden, Colorado 80401 USA Geology deals with three-dimensional data. Geoscientists are concerned with three dimensional spatial observations, measurements, and explanations of a great variety of phenomena. The representation of three-dimensional data has always been a problem. Prior to computers, graphical displays involved specialized maps, cross-sections, fence diagrams, and geometrical constructions such as stereonets. All were designed to portray three-dimensional relationships on two-dimensional paper products, and all were time consuming to develop. Until recently, computers were of little assistance to three-dimensional data handling and representation problems. Memory was too expensive to handle the huge amounts of data required by three-dimensional assessments; computational speeds were too slow to perform the necessary calculations within a reasonable time; and graphical displays had too Iowa resolution or were much too expensive to produce useful visualizations. Much experience was gained with two-dimensional geographic information systems (GIS), which were applied to many land-use management and resource assessment problems. The two-dimensional GIS field matured rapidly in the late 1980's and became widely accepted. The advent of the modern computer workstation, with its enhanced memory and graphical capabilities at ever more affordable prices, has largely overcome these earlier constraints.

The book presents a comprehensive overview of various aspects of three-dimensional geometry that can be experienced on a daily basis. By covering the wide range of topics — from the psychology of spatial perception to the principles of 3D modelling and printing, from the invention of perspective by Renaissance artists to the art of Origami, from polyhedral shapes to the theory of knots, from patterns in space to the problem of optimal packing, and from the problems of cartography to the geometry of solar and lunar eclipses — this book provides deep insight into phenomena related to the geometry of space and exposes incredible nuances that can enrich our lives.The book is aimed at the general readership and provides more than 420 color illustrations that support the explanations and replace formal mathematical arguments with clear graphical representations.

We live in a time of great change. In the electronics world, the last several decades have seen unprecedented growth and advancement, described by Moore’s law. This observation stated that transistor density in integrated circuits doubles every 1. 5–2 years. This came with the simultaneous improvement of individual device perf- mance as well as the reduction of device power such that the total power of the resulting ICs remained under control. No trend remains constant forever, and this is unfortunately the case with Moore’s law. The trouble began a number of years ago when CMOS devices were no longer able to proceed along the classical scaling trends. Key device parameters such as gate oxide thickness were simply no longer able to scale. As a result, device o- state currents began to creep up at an alarming rate. These continuing problems with classical scaling have led to a leveling off of IC clock speeds to the range of several GHz. Of course, chips can be clocked higher but the thermal issues become unmanageable. This has led to the recent trend toward microprocessors with mul- ple cores, each running at a few GHz at the most. The goal is to continue improving performance via parallelism by adding more and more cores instead of increasing speed. The challenge here is to ensure that general purpose codes can be ef?ciently parallelized. There is another potential solution to the problem of how to improve CMOS technology performance: three-dimensional integrated circuits (3D ICs).