IC designers appraise currently MOS transistor geometries and currents to compromise objectives like gain-bandwidth, slew-rate, dynamic range, noise, non-linear distortion, etc. Making optimal choices is a difficult task. How to minimize for instance the power consumption of an operational amplifier without too much penalty regarding area while keeping the gain-bandwidth unaffected in the same time? Moderate inversion yields high gains, but the concomitant area increase adds parasitics that restrict bandwidth. Which methodology to use in order to come across the best compromise(s)? Is synthesis a mixture of design experience combined with cut and tries or is it a constrained multivariate optimization problem, or a mixture? Optimization algorithms are attractive from a system perspective of course, but what about low-voltage low-power circuits, requiring a more physical approach? The connections amid transistor physics and circuits are intricate and their interactions not always easy to describe in terms of existing software packages. The gm/ID synthesis methodology is adapted to CMOS analog circuits for the transconductance over drain current ratio combines most of the ingredients needed in order to determine transistors sizes and DC currents.

IC designers appraise currently MOS transistor geometries and currents to compromise objectives like gain-bandwidth, slew-rate, dynamic range, noise, non-linear distortion, etc. Making optimal choices is a difficult task. How to minimize for instance the power consumption of an operational amplifier without too much penalty regarding area while keeping the gain-bandwidth unaffected in the same time? Moderate inversion yields high gains, but the concomitant area increase adds parasitics that restrict bandwidth. Which methodology to use in order to come across the best compromise(s)? Is synthesis a mixture of design experience combined with cut and tries or is it a constrained multivariate optimization problem, or a mixture? Optimization algorithms are attractive from a system perspective of course, but what about low-voltage low-power circuits, requiring a more physical approach? The connections amid transistor physics and circuits are intricate and their interactions not always easy to describe in terms of existing software packages. The gm/ID synthesis methodology is adapted to CMOS analog circuits for the transconductance over drain current ratio combines most of the ingredients needed in order to determine transistors sizes and DC currents.

Discover a fresh approach to efficient and insight-driven analog integrated circuit design in nanoscale-CMOS with this hands-on guide. Expert authors present a sizing methodology that employs SPICE-generated lookup tables, enabling close agreement between hand analysis and simulation. This enables the exploration of analog circuit tradeoffs using the gm/ID ratio as a central variable in script-based design flows, and eliminates time-consuming iterations in a circuit simulator. Supported by downloadable MATLAB code, and including over forty detailed worked examples, this book will provide professional analog circuit designers, researchers, and graduate students with the theoretical know-how and practical tools needed to acquire a systematic and re-use oriented design style for analog integrated circuits in modern CMOS.

This book explains the application of recent advances in computational intelligence – algorithms, design methodologies, and synthesis techniques – to the design of integrated circuits and systems. It highlights new biasing and sizing approaches and optimization techniques and their application to the design of high-performance digital, VLSI, radio-frequency, and mixed-signal circuits and systems. This first of two related volumes addresses the design of analog and mixed-signal (AMS) and radio-frequency (RF) circuits, with 17 chapters grouped into parts on analog and mixed-signal applications, and radio-frequency design. It will be of interest to practitioners and researchers in computer science and electronics engineering engaged with the design of electronic circuits.

Over the past few decades, devices and technologies have been significantly miniaturized from one generation to the next, providing far more potential in a much smaller package. The smallest of these recently developed tools are miniscule enough to be invisible to the naked eye. Nanotechnology: Concepts, Methodologies, Tools, and Applications describes some of the latest advances in microscopic technologies in fields as diverse as biochemistry, materials science, medicine, and electronics. Through its investigation of theories, applications, and new developments in the nanotechnology field, this impressive reference source will serve as a valuable tool for researchers, engineers, academics, and students alike.

Chip-integrated power management solutions are a must for ultra-low power systems. This enables not only the optimization of innovative sensor applications. It is also essential for integration and miniaturization of energy harvesting supply strategies of portable and autonomous monitoring systems. The book particularly addresses interfaces for energy harvesting, which are the key element to connect micro transducers to energy storage elements. Main features of the book are: - A comprehensive technology and application review, basics on transducer mechanics, fundamental circuit and control design, prototyping and testing, up to sensor system supply and applications. - Novel interfacing concepts - including active rectifiers, MPPT methods for efficient tracking of DC as well as AC sources, and a fully-integrated charge pump for efficient maximum AC power tracking at sub-100μW ultra-low power levels. The chips achieve one of widest presented operational voltage range in standard CMOS technology: 0.44V to over 4.1V. - Two special chapters on analog circuit design – it studies benefits and obstacles on implemented chip prototypes with three goals: ultra- low power, wide supply voltage range, and integration with standard technologies. Alternative design approaches are pursued using bulk-input transistor stages in forward-bias operation for amplifiers, modulators, and references. - Comprehensive Appendix – with additional fundamental analysis, design and scaling guidelines, circuit implementation tables and dimensions, schematics, source code listings, bill of material, etc. The discussed prototypes and given design guidelines are tested with real vibration transducer devices. The intended readership is graduate students in advanced courses, academics and lecturers, R&D engineers.

This volume comprises a selection of works presented at the Numerical and Evolutionary Optimization (NEO 2016) workshop held in September 2016 in Tlalnepantla, Mexico. The development of powerful search and optimization techniques is of great importance in today’s world and requires researchers and practitioners to tackle a growing number of challenging real-world problems. In particular, there are two well-established and widely known fields that are commonly applied in this area: (i) traditional numerical optimization techniques and (ii) comparatively recent bio-inspired heuristics. Both paradigms have their unique strengths and weaknesses, allowing them to solve some challenging problems while still failing in others. The goal of the NEO workshop series is to bring together experts from these and related fields to discuss, compare and merge their complementary perspectives in order to develop fast and reliable hybrid methods that maximize the strengths and minimize the weaknesses of the underlying paradigms. In doing so, NEO promotes the development of new techniques that are applicable to a broader class of problems. Moreover, NEO fosters the understanding and adequate treatment of real-world problems particularly in emerging fields that affect all of us, such as healthcare, smart cities, big data, among many others. The extended papers presented in the book contribute to achieving this goal.