Abstract: "In this correspondence, we propose a design and analysis technique for a class of Multistage Interconnection Networks (MINs). This class of MINs have finite buffers at the input side of their switch elements and operate in a synchronous packet-switched mode. We first examine the important issue of different clock periods in the synchronous MIN analysis. Then we analyze our 'small cycle' design with a simple analytical model and compare the results with that of a somewhat standard 'big cycle' model that is currently used. The significant performance improvement of our model is shown based on various clock width, data width, and buffer length."

Abstract: "This paper concerns the analysis of the Split-buffered Multistage Interconnection Networks (SMINs) under the favorite input load. The favorite load is a typical nonuniform traffic pattern which includes the uniform load as its special case. A new analytical model of SMINs under the favorite load is developed. The analytical results are validated through simulations. It is shown that the SMINs generally perform better under the favorite load than the SMINs under the uniform load. The analytical model itself also shows potential for evaluating other high performance switch designs."