Moore's law has driven the scaling of digital electronic devices' dimensions and performances over the last 40 years. As a result, logic components in a microprocessor have shown dramatic performance improvement. On the other hand, an on-chip interconnect which was considered only as a parasitic load before 1990s became the real performance bottleneck due to its extremely reduced cross section dimension. Now, on-chip global interconnect with conventional Cu/low-k and delay optimized repeater scheme faces great challenges in the nanometer regime, imposing problems of slower delay, higher power dissipation and limited bandwidth. Carbon based materials such as carbon nanotubes and graphene nanoribbons, and optical interconnect have been proposed for the alternate solution for the future nodes due to their special physical characteristics. This dissertation investigates the basic physical properties of novel materials for future interconnect, and describes the analytical and numerical models of local and global wire system based on new materials and novel signaling paradigms. This work also compares their basic performance metrics and circuit architectures to cope with the interconnect performance bottlenecks. We quantify the performance of these novel interconnects and compare them with Cu/low-k wires for future high-performance ICs.

The book provides accurate FDTD models for on-chip interconnects, covering most recent advancements in materials and design. Furthermore, depending on the geometry and physical configurations, different electrical equivalent models for CNT and GNR based interconnects are presented. Based on the electrical equivalent models the performance comparison among the Cu, CNT and GNR-based interconnects are also discussed in the book. The proposed models are validated with the HSPICE simulations. The book introduces the current research scenario in the modeling of on-chip interconnects. It presents the structure, properties, and characteristics of graphene based on-chip interconnects and the FDTD modeling of Cu based on-chip interconnects. The model considers the non-linear effects of CMOS driver as well as the transmission line effects of interconnect line that includes coupling capacitance and mutual inductance effects. In a more realistic manner, the proposed model includes the effect of width-dependent MFP of the MLGNR while taking into account the edge roughness.

Noise Coupling is the root-cause of the majority of Systems on Chip (SoC) product fails. The book discusses a breakthrough substrate coupling analysis flow and modelling toolset, addressing the needs of the design community. The flow provides capability to analyze noise components, propagating through the substrate, the parasitic interconnects and the package. Using this book, the reader can analyze and avoid complex noise coupling that degrades RF and mixed signal design performance, while reducing the need for conservative design practices. With chapters written by leading international experts in the field, novel methodologies are provided to identify noise coupling in silicon. It additionally features case studies that can be found in any modern CMOS SoC product for mobile communications, automotive applications and readout front ends.

The proceedings of SocProS 2015 will serve as an academic bonanza for scientists and researchers working in the field of Soft Computing. This book contains theoretical as well as practical aspects using fuzzy logic, neural networks, evolutionary algorithms, swarm intelligence algorithms, etc., with many applications under the umbrella of ‘Soft Computing’. The book will be beneficial for young as well as experienced researchers dealing across complex and intricate real world problems for which finding a solution by traditional methods is a difficult task. The different application areas covered in the proceedings are: Image Processing, Cryptanalysis, Industrial Optimization, Supply Chain Management, Newly Proposed Nature Inspired Algorithms, Signal Processing, Problems related to Medical and Health Care, Networking Optimization Problems, etc.

The brief primarily focuses on the performance analysis of CNT based interconnects in current research scenario. Different CNT structures are modeled on the basis of transmission line theory. Performance comparison for different CNT structures illustrates that CNTs are more promising than Cu or other materials used in global VLSI interconnects. The brief is organized into five chapters which mainly discuss: (1) an overview of current research scenario and basics of interconnects; (2) unique crystal structures and the basics of physical properties of CNTs, and the production, purification and applications of CNTs; (3) a brief technical review, the geometry and equivalent RLC parameters for different single and bundled CNT structures; (4) a comparative analysis of crosstalk and delay for different single and bundled CNT structures; and (5) various unique mixed CNT bundle structures and their equivalent electrical models.

This book explains the application of recent advances in computational intelligence – algorithms, design methodologies, and synthesis techniques – to the design of integrated circuits and systems. It highlights new biasing and sizing approaches and optimization techniques and their application to the design of high-performance digital, VLSI, radio-frequency, and mixed-signal circuits and systems. This second of two related volumes addresses digital and network designs and applications, with 12 chapters grouped into parts on digital circuit design, network optimization, and applications. It will be of interest to practitioners and researchers in computer science and electronics engineering engaged with the design of electronic circuits.

This Second Edition focuses on emerging topics and advances in the field of VLSI interconnections In the decade since High-Speed VLSI Interconnections was first published, several major developments have taken place in the field. Now, updated to reflect these advancements, this Second Edition includes new information on copper interconnections, nanotechnology circuit interconnects, electromigration in the copper interconnections, parasitic inductances, and RLC models for comprehensive analysis of interconnection delays and crosstalk. Each chapter is designed to exist independently or as a part of one coherent unit, and several appropriate exercises are provided at the end of each chapter, challenging the reader to gain further insight into the contents being discussed. Chapter subjects include: * Preliminary Concepts * Parasitic Resistances, Capacitances, and Inductances * Interconnection Delays * Crosstalk Analysis * Electromigration-Induced Failure Analysis * Future Interconnections High-Speed VLSI Interconnections, Second Edition is an indispensable reference for high-speed VLSI designers, RF circuit designers, and advanced students of electrical engineering.