Issues relating to the high-K gate dielectric are among the greatest challenges for the evolving International Technology Roadmap for Semiconductors (ITRS). More than just an historical overview, this book will assess previous and present approaches related to scaling the gate dielectric and their impact, along with the creative directions and forthcoming challenges that will define the future of gate dielectric scaling technology. Topics include: an extensive review of Moore's Law, the classical regime for SiO2 gate dielectrics; the transition to silicon oxynitride gate dielectrics; the transition to high-K gate dielectrics (including the drive towards equivalent oxide thickness in the single-digit nanometer regime); and future directions and issues for ultimate technology generation scaling. The vision, wisdom, and experience of the team of authors will make this book a timely, relevant, and interesting, resource focusing on fundamentals of the 45 nm Technology Generation and beyond.

This issue covers in detail all aspects of the physics and the technology of high dielectric constant gate stacks, including high mobility substrates, high dielectric constant materials, processing, metals for gate electrodes, interfaces, physical, chemical, and electrical characterization, gate stack reliability, and DRAM and non-volatile memories.

Semiconductor Memories and Systems provides a comprehensive overview of the current state of semiconductor memory at the technology and system levels. After an introduction on market trends and memory applications, the book focuses on mainstream technologies, illustrating their current status, challenges and opportunities, with special attention paid to scalability paths. Technologies discussed include static random access memory (SRAM), dynamic random access memory (DRAM), non-volatile memory (NVM), and NAND flash memory. Embedded memory and requirements and system level needs for storage class memory are also addressed. Each chapter covers physical operating mechanisms, fabrication technologies, and the main challenges to scalability.Finally, the work reviews the emerging trends for storage class memory, mainly focusing on the advantages and opportunities of phase change based memory technologies. - Features contributions from experts from leading companies in semiconductor memory - Discusses physical operating mechanisms, fabrication technologies and paths to scalability for current and emerging semiconductor memories - Reviews primary memory technologies, including SRAM, DRAM, NVM and NAND flash memory - Includes emerging storage class memory technologies such as phase change memory

Interest in latchup is being renewed with the evolution of complimentary metal-oxide semiconductor (CMOS) technology, metal-oxide-semiconductor field-effect transistor (MOSFET) scaling, and high-level system-on-chip (SOC) integration. Clear methodologies that grant protection from latchup, with insight into the physics, technology and circuit issues involved, are in increasing demand. This book describes CMOS and BiCMOS semiconductor technology and their sensitivity to present day latchup phenomena, from basic over-voltage and over-current conditions, single event latchup (SEL) and cable discharge events (CDE), to latchup domino phenomena. It contains chapters focusing on bipolar physics, latchup theory, latchup and guard ring characterization structures, characterization testing, product level test systems, product level testing and experimental results. Discussions on state-of-the-art semiconductor processes, design layout, and circuit level and system level latchup solutions are also included, as well as: latchup semiconductor process solutions for both CMOS to BiCMOS, such as shallow trench, deep trench, retrograde wells, connecting implants, sub-collectors, heavily-doped buried layers, and buried grids – from single- to triple-well CMOS; practical latchup design methods, automated and bench-level latchup testing methods and techniques, latchup theory of logarithm resistance space, generalized alpha (a) space, beta (b) space, new latchup design methods– connecting the theoretical to the practical analysis, and; examples of latchup computer aided design (CAD) methodologies, from design rule checking (DRC) and logical-to-physical design, to new latchup CAD methodologies that address latchup for internal and external latchup on a local as well as global design level. Latchup acts as a companion text to the author’s series of books on ESD (electrostatic discharge) protection, serving as an invaluable reference for the professional semiconductor chip and system-level ESD engineer. Semiconductor device, process and circuit designers, and quality, reliability and failure analysis engineers will find it informative on the issues that confront modern CMOS technology. Practitioners in the automotive and aerospace industries will also find it useful. In addition, its academic treatment will appeal to both senior and graduate students with interests in semiconductor process, device physics, computer aided design and design integration.

This book reviews a range of quantum phenomena in novel nanoscale transistors called FinFETs, including quantized conductance of 1D transport, single electron effect, tunneling transport, etc. The goal is to create a fundamental bridge between quantum FinFET and nanotechnology to stimulate readers' interest in developing new types of semiconductor technology. Although the rapid development of micro-nano fabrication is driving the MOSFET downscaling trend that is evolving from planar channel to nonplanar FinFET, silicon-based CMOS technology is expected to face fundamental limits in the near future. Therefore, new types of nanoscale devices are being investigated aggressively to take advantage of the quantum effect in carrier transport. The quantum confinement effect of FinFET at room temperatures was reported following the breakthrough to sub-10nm scale technology in silicon nanowires. With chapters written by leading scientists throughout the world, Toward Quantum FinFET provides a comprehensive introduction to the field as well as a platform for knowledge sharing and dissemination of the latest advances. As a roadmap to guide further research in an area of increasing importance for the future development of materials science, nanofabrication technology, and nano-electronic devices, the book can be recommended for Physics, Electrical Engineering, and Materials Science departments, and as a reference on micro-nano electronic science and device design. Offers comprehensive coverage of novel nanoscale transistors with quantum confinement effect Provides the keys to understanding the emerging area of the quantum FinFET Written by leading experts in each research area Describes a key enabling technology for research and development of nanofabrication and nanoelectronic devices