The State of Memory Technology Over the past decade there has been rapid growth in the speed of micropro cessors. CPU speeds are approximately doubling every eighteen months, while main memory speed doubles about every ten years. The International Tech nology Roadmap for Semiconductors (ITRS) study suggests that memory will remain on its current growth path. The ITRS short-and long-term targets indicate continued scaling improvements at about the current rate by 2016. This translates to bit densities increasing at two times every two years until the introduction of 8 gigabit dynamic random access memory (DRAM) chips, after which densities will increase four times every five years. A similar growth pattern is forecast for other high-density chip areas and high-performance logic (e.g., microprocessors and application specific inte grated circuits (ASICs)). In the future, molecular devices, 64 gigabit DRAMs and 28 GHz clock signals are targeted. Although densities continue to grow, we still do not see significant advances that will improve memory speed. These trends have created a problem that has been labeled the Memory Wall or Memory Gap.

Die Bandbreite und Zugriffszeit traditioneller DRAMs reicht nicht mehr aus, um mit der Geschwindigkeit moderner Mikroprozessoren Schritt zu halten. Daher baut man verstärkt Hochleistungs-Speicherchips, deren neue Generation das Thema dieses Buches bildet. Die Autorin, eine international anerkannte Spezialistin, diskutiert objektiv und herstellerunabhängig Technologien wie DDR DRAMs, CiDDR DRAMs, SL=DRAM, Direct Rambus, SSTL Interfaces und MP-DRAMs. Der aktuellste verfügbare Beitrag zu einem enorm wichtigen Thema! (12/98)

Is your memory hierarchy stopping your microprocessor from performing at the high level it should be? Memory Systems: Cache, DRAM, Disk shows you how to resolve this problem. The book tells you everything you need to know about the logical design and operation, physical design and operation, performance characteristics and resulting design trade-offs, and the energy consumption of modern memory hierarchies. You learn how to to tackle the challenging optimization problems that result from the side-effects that can appear at any point in the entire hierarchy.As a result you will be able to design and emulate the entire memory hierarchy. - Understand all levels of the system hierarchy -Xcache, DRAM, and disk. - Evaluate the system-level effects of all design choices. - Model performance and energy consumption for each component in the memory hierarchy.

This book constitutes the refereed joint proceedings of ten international workshops held in conjunction with the 4th International Symposium on Parallel and Distributed Processing and Applications, ISPA 2006, held in Sorrento, Italy in December 2006. It contains 116 papers that contribute to enlarging the spectrum of the more general topics treated in the ISPA 2006 main conference.