This book consists of four chapters to address at different modeling levels for different nanoscale MOS structures (Single- and Multi-Gate MOSFETs). The collection of these chapters in the book are attempted to provide a comprehensive coverage on the different levels of electrostatics and transport modeling for these devices, and relationships between them. In particular, the issue of quantum transport approaches, analytical predictive 2D/3D modeling and design-oriented compact modeling. It should be of interests to researchers working on modeling at any level, to provide them with a clear explanation of theapproaches used and the links with modeling techniques for either higher or lower levels.

Compact Models for Integrated Circuit Design: Conventional Transistors and Beyond provides a modern treatise on compact models for circuit computer-aided design (CAD). Written by an author with more than 25 years of industry experience in semiconductor processes, devices, and circuit CAD, and more than 10 years of academic experience in teaching compact modeling courses, this first-of-its-kind book on compact SPICE models for very-large-scale-integrated (VLSI) chip design offers a balanced presentation of compact modeling crucial for addressing current modeling challenges and understanding new models for emerging devices. Starting from basic semiconductor physics and covering state-of-the-art device regimes from conventional micron to nanometer, this text: Presents industry standard models for bipolar-junction transistors (BJTs), metal-oxide-semiconductor (MOS) field-effect-transistors (FETs), FinFETs, and tunnel field-effect transistors (TFETs), along with statistical MOS models Discusses the major issue of process variability, which severely impacts device and circuit performance in advanced technologies and requires statistical compact models Promotes further research of the evolution and development of compact models for VLSI circuit design and analysis Supplies fundamental and practical knowledge necessary for efficient integrated circuit (IC) design using nanoscale devices Includes exercise problems at the end of each chapter and extensive references at the end of the book Compact Models for Integrated Circuit Design: Conventional Transistors and Beyond is intended for senior undergraduate and graduate courses in electrical and electronics engineering as well as for researchers and practitioners working in the area of electron devices. However, even those unfamiliar with semiconductor physics gain a solid grasp of compact modeling concepts from this book.

Microelectronics is one of the most rapidly changing scientific fields today. The tendency to shrink devices as far as possible results in extremely small devices which can no longer be described using simple analytical models. This book covers various aspects of advanced device modeling and simulation. As such it presents extensive reviews and original research by outstanding scientists. The bulk of the book is concerned with the theory of classical and quantum-mechanical transport modeling, based on macroscopic, spherical harmonics and Monte Carlo methods.

Nanotechnology, science, and engineering spearhead the 21st century revolution that is leading to fundamental breakthroughs in the way materials, devices, and systems are understood, designed, made, and used. With contributions from a host of world-class experts and pioneers in the field, this handbook sets forth the fundamentals of nanoelectromech

Most of the recent texts on compact modeling are limited to a particular class of semiconductor devices and do not provide comprehensive coverage of the field. Having a single comprehensive reference for the compact models of most commonly used semiconductor devices (both active and passive) represents a significant advantage for the reader. Indeed, several kinds of semiconductor devices are routinely encountered in a single IC design or in a single modeling support group. Compact Modeling includes mostly the material that after several years of IC design applications has been found both theoretically sound and practically significant. Assigning the individual chapters to the groups responsible for the definitive work on the subject assures the highest possible degree of expertise on each of the covered models.

As silicon CMOS technology continues to scale down its minimum critical dimension, it becomes increasingly difficult to enhance device switching speed due to fundamental limitations. Innovations in device structure and materials are pursued to accommodate improvement in performance as well as reduction in transistor size. For beyond-22-nm CMOS technology, III-V channel FETs are considered as a compelling candidate for extending the device scaling limit of low-power and high-speed operation, owing to their superb carrier transport properties and recent experimental advancements. In this thesis, device simulation, compact modeling, circuit design, circuit performance assessment and estimation of III-V logic transistors are carried out to study key considerations such as device pitch, parasitics, and the importance of PMOS for circuit-level performance. To effectively connect device characteristics with circuit design, a physics-based compact model for digital logic is constructed. The model encompasses effects such as field-confined and spatially-confined trapezoidal quantum well sub-band energies, gate leakage tunneling current and parasitic capacitance. The developed compact model contains only three fitting parameters and is verified by experiment and circuit simulations. The compact model enables other bodies of work for the purpose of circuit-level design and performance estimation. To demonstrate the capability of the model in a circuit environment we apply the compact model to composite circuits such as FO4 inverter chains and SRAM cache to evaluate and project performance and power trends for beyond-22-nm technology.

The first book to deal with a broad spectrum of process and device design, and modeling issues related to semiconductor devices, bridging the gap between device modelling and process design using TCAD. Presents a comprehensive perspective of emerging fields and covers topics ranging from materials to fabrication, devices, modelling and applications. Aimed at research-and-development engineers and scientists involved in microelectronics technology and device design via Technology CAD, and TCAD engineers and developers.