"...offers a tutorial guide to IC designers who want to move to the next level of chip design by unlocking the secrets of signal integrity." —Jake Buurma, Senior Vice President, Worldwide Research & Development, Cadence Design Systems, Inc. Covers signal integrity effects in high performance Radio Frequency (RF) IC Brings together research papers from the past few years that address the broad range of issues faced by IC designers and CAD managers now and in the future A Wiley-IEEE Press publication

In the early days of VLSI, the design of the power distribution for an integrated cir cuit was rather simple. Power distribution --the design of the geometric topology for the network of wires that connect the various power supplies, the widths of the indi vidual segments for each of these wires, the number and location of the power I/O pins around the periphery of the chip --was simple because the chips were simpler. Few available wiring layers forced floorplans that allowed simple, planar (non-over lapping) power networks. Lower speeds and circuit density made the choice of the wire widths easier: we made them just fat enough to avoid resistive voltage drops due to switching currents in the supply network. And we just didn't need enormous num bers of power and ground pins on the package for the chips to work. It's not so simple any more. Increased integration has forced us to focus on reliability concerns such as metal elec tromigration, which affects wire sizing decisions in the power network. Extra metal layers have allowed more flexibility in the topological layout of the power networks.

by Kurt Keutzer Those looking for a quick overview of the book should fast-forward to the Introduction in Chapter 1. What follows is a personal account of the creation of this book. The challenge from Earl Killian, formerly an architect of the MIPS processors and at that time Chief Architect at Tensilica, was to explain the significant performance gap between ASICs and custom circuits designed in the same process generation. The relevance of the challenge was amplified shortly thereafter by Andy Bechtolsheim, founder of Sun Microsystems and ubiquitous investor in the EDA industry. At a dinner talk at the 1999 International Symposium on Physical Design, Andy stated that the greatest near-term opportunity in CAD was to develop tools to bring the performance of ASIC circuits closer to that of custom designs. There seemed to be some synchronicity that two individuals so different in concern and character would be pre-occupied with the same problem. Intrigued by Earl and Andy’s comments, the game was afoot. Earl Killian and other veterans of microprocessor design were helpful with clues as to the sources of the performance discrepancy: layout, circuit design, clocking methodology, and dynamic logic. I soon realized that I needed help in tracking down clues. Only at a wonderful institution like the University of California at Berkeley could I so easily commandeer an ab- bodied graduate student like David Chinnery with a knowledge of architecture, circuits, computer-aided design and algorithms.

"An excellent introduction to the SiGe BiCMOS technology, from the underlying device physics to current applications." -Ron Wilson, EETimes "SiGe technology has demonstrated the ability to provide excellent high-performance characteristics with very low noise, at high power gain, and with excellent linearity. This book is a comprehensive review of the technology and of the design methods that go with it." -Alberto Sangiovanni-Vincentelli Professor, University of California, Berkeley Cofounder, Chief Technology Officer, Member of Board Cadence Design Systems Inc. Filled with in-depth insights and expert advice, Silicon Germanium covers all the key aspects of this technology and its applications. Beginning with a brief introduction to and historical perspective of IBM's SiGe technology, this comprehensive guide quickly moves on to: * Detail many of IBM's SiGe technology development programs * Explore IBM's approach to device modeling and characterization-including predictive TCAD modeling * Discuss IBM's design automation and signal integrity knowledge and implementation methodologies * Illustrate design applications in a variety of IBM's SiGe technologies * Highlight details of highly integrated SiGe BiCMOS system-on-chip (SOC) design Written for RF/analog and mixed-signal designers, CAD designers, semiconductor students, and foundry process engineers worldwide, Silicon Germanium provides detailed insight into the modeling and design automation requirements for leading-edge RF/analog and mixed-signal products, and illustrates in-depth applications that can be implemented using IBM's advanced SiGe process technologies and design kits. "This volume provides an excellent introduction to the SiGe BiCMOS technology, from the underlying device physics to current applications. But just as important is the window the text provides into the infrastructure-the process development, device modeling, and tool development." -Ron Wilson Silicon Engineering Editor, EETimes "This book chronicles the development of SiGe in detail, provides an in-depth look at the modeling and design automation requirements for making advanced applications using SiGe possible, and illustrates such applications as implemented using IBM's process technologies and design methods." -John Kelly Senior Vice President and Group Executive, Technology Group, IBM

This is the book version of a special issue of the International Journal of High Speed Electronics and Systems, reviewing recent work in the field of compound semiconductor integrated circuits. There are fourteen invited papers covering a wide range of applications, frequencies and materials. These papers deal with digital, analog, microwave and millimeter-wave technologies, devices and integrated circuits for wireline fiber-optic lightwave transmissions, and wireless radio-frequency microwave and millimeter-wave communications. In each case, the market is young and experiencing rapid growth for both commercial and millitary applications. Many new semiconductor technologies compete for these new markets, leading to an alphabet soup of semiconductor materials described in these papers. The book also includes three papers focused on radiation effects and reliability in III-V semiconductor electronics, which are useful for reference and future directions. Moreover, reliability is covered in several papers separately for certain process technologies. Contents: Present and Future of High-Speed Compound Semiconductor IC''s (T Otsuji); The Transforming MMIC (E J Martinez); Distributed Amplifier for Fiber-Optic Communication Systems (H Shigematsu et al.); Microwave GaN-Based Power Transistors on Large-Scale Silicon Wafers (S Manohar et al.); Radiation Effects in High Speed III-V Integrated Circuits (T R Weatherford); Radiation Effects in III-V Semiconductor Electronics (B D Weaver et al.); Reliability and Radiation Hardness of Compound Semiconductors (S A Kayali & A H Johnston); and other papers. Readership: Engineers, scientists and graduate students working on high speed electronics and systems, and in the area of compound semiconductor integrated circuits.

Model order reduction (MOR) techniques reduce the complexity of VLSI designs, paving the way to higher operating speeds and smaller feature sizes. This book presents a systematic introduction to, and treatment of, the key MOR methods employed in general linear circuits, using real-world examples to illustrate the advantages and disadvantages of each algorithm. Following a review of traditional projection-based techniques, coverage progresses to more advanced MOR methods for VLSI design, including HMOR, passive truncated balanced realization (TBR) methods, efficient inductance modeling via the VPEC model, and structure-preserving MOR techniques. Where possible, numerical methods are approached from the CAD engineer's perspective, avoiding complex mathematics and allowing the reader to take on real design problems and develop more effective tools. With practical examples and over 100 illustrations, this book is suitable for researchers and graduate students of electrical and computer engineering, as well as practitioners working in the VLSI design industry.

Current-Mode digital circuits have been extensively analyzed and used since the early days of digital ICs. In particular, bipolar Current-Mode digital circuits emerged as an approach to realize digital circuits with the highest speed. Together with its speed performance, CMOS Current-Mode logic has been rediscovered to allow logic gates implementations which, in contrast to classical VLSI CMOS digital circuits, have the feature of low noise level generation. Thus, CMOS Current-Mode gates can be efficiently used inside analog and mixed-signal ICs, which require a low noise silicon environment. For these reasons, until today, many works and results have been published which reinforce the importance of Current-Mode digital circuits. In the topic of Current-Mode digital circuits, the authors spent a lot of effort in the last six years, and their original results highly enhanced both the modeling and the related design methodologies. Since the fundamental Current-Mode logic building block is the classical differential amplifier, the winning idea, that represents the starting point of the authors’ research, was to change the classical point of view typically followed in the investigation and design of Current-Mode digital circuits. In particular, they properly exploited classical paradigms developed and used in the analog circuit domain (a topic in which one of the authors maturated a great experience).