Modeling and Simulation of High Speed VLSI Interconnects brings together in one place important contributions and state-of-the-art research results in this rapidly advancing area. Modeling and Simulation of High Speed VLSI Interconnects serves as an excellent reference, providing insight into some of the most important issues in the field.

The intense drive for signal integrity has been at the forefront ofrapid and new developments in CAD algorithms. Thousands ofengineers, intent on achieving the best design possible, use SPICE on a daily basis for analog simulation and general circuit analysis. But the strained demand for high data speeds, coupled with miniaturizationon an unprecedented scale, has highlighted the previously negligible effects of interconnects; effects which are not always handled appro priately by the present levels of SPICE. Signals at these higher speeds may be degraded by long interconnect lengths compared to the increasingly shorter sig nal rise times. Interconnect structures can be diverse (pins, connectors, leads, microstrips, striplines, etc. ) and present at any of the hierarchical packaging levels: integrated circuits, printed circuit boards, multi-chip modules or sys tem backplanes. Analysis of these effects in any CAD package has become a necessity. Asymptotic waveform evaluation (AWE) and other moment matching tech niques have recently proven useful in the analysis of interconnect structures and various networks containing large linear structures with nonlinear termi nations. Previously, all that was available to the designer was a full SPICE simulation or a quick but uncertain timing estimation. Moment matching, used in linear systems analysis as a method of model reduction, describes a method to extract a small set of dominant poles from a large network. The information is obtained from the Taylor series coefficients (moments) of that system.