One of the main problems in chip design is the enormous number of possible combinations of individual chip elements within a system, and the problem of their compatibility. The recent application of data structures, efficient algorithms, and ordered binary decision diagrams (OBDDs) has proven vital in designing the computer chips of tomorrow. This book provides an introduction to the foundations of this interdisciplinary research area, emphasizing its applications in computer aided circuit design.

A logic view of 0-1 integer programming problems, providing new insights into the structure of problems that can lead the researcher to more effective solution techniques depending on the problem class. Operations research techniques are integrated into a logic programming environment. The first monographic treatment that begins to unify these two methodological approaches. Logic-based methods for modelling and solving combinatorial problems have recently started to play a significant role in both theory and practice. The application of logic to combinatorial problems has a dual aspect. On one hand, constraint logic programming allows one to declaratively model combinatorial problems over an appropriate constraint domain, the problems then being solved by a corresponding constraint solver. Besides being a high-level declarative interface to the constraint solver, the logic programming language allows one also to implement those subproblems that cannot be naturally expressed with constraints. On the other hand, logic-based methods can be used as a constraint solving technique within a constraint solver for combinatorial problems modelled as 0-1 integer programs.

This book is intended as an innovative overview of current formal verification methods, combined with an in-depth analysis of some advanced techniques to improve the scalability of these methods, and close the gap between design and verification in computer-aided design. Formal Verification: Scalable Hardware Verification with Symbolic Simulation explains current formal verification methods and provides an in-depth analysis of some advanced techniques to improve the scalability of these methods and close the gap between design and verification in computer-aided design. It provides the theoretical background required to present such methods and advanced techniques, i.e. Boolean function representations, models of sequential networks and, in particular, some novel algorithms to expose the disjoint support decompositions of Boolean functions, used in one of the scalable approaches.

This book constitutes the refereed proceedings of the 12th International Conference on Theory and Applications of Satisfiability Testing, SAT 2009, held in Swansea, UK, in June/July 2009. The 34 revised full papers presented together with 11 revised short papers and 2 invited talks were carefully selected from 86 submissions. The papers are organized in topical sections on applications of SAT, complexity theory, structures for SAT, resolution and SAT, translations to CNF, techniques for conflict-driven SAT Solvers, solving SAT by local search, hybrid SAT solvers, automatic adaption of SAT solvers, stochastic approaches to SAT solving, QBFs and their representations, optimization algorithms, distributed and parallel solving.

The size of technically producible integrated circuits increases continuously. But the ability to design and verify these circuits does not keep up with this development. Therefore today’s design flow has to be improved to achieve a higher productivity. In Robustness and Usability in Modern Design Flows the current design methodology and verification methodology are analyzed, a number of deficiencies are identified and solutions suggested. Improvements in the methodology as well as in the underlying algorithms are proposed. An in-depth presentation of preliminary concepts makes the book self-contained. Based on this foundation major design problems are targeted. In particular, a complete tool flow for Synthesis for Testability of SystemC descriptions is presented. The resulting circuits are completely testable and test pattern generation in polynomial time is possible. Verification issues are covered in even more detail. A whole new paradigm for formal design verification is suggested. This is based upon design understanding, the automatic generation of properties and powerful tool support for debugging failures. All these new techniques are empirically evaluated and experimental results are provided. As a result, an enhanced design flow is created that provides more automation (i.e. better usability) and reduces the probability of introducing conceptual errors (i.e. higher robustness).