Due to the ever increasing electric fields in scaled CMOS devices, reliability is becoming a showstopper for further scaled technology nodes. Although several groups have already demonstrated functional Si channel devices with aggressively scaled Equivalent Oxide Thickness (EOT) down to 5Å, a 10 year reliable device operation cannot be guaranteed anymore due to severe Negative Bias Temperature Instability. This book focuses on the reliability of the novel (Si)Ge channel quantum well pMOSFET technology. This technology is being considered for possible implementation in next CMOS technology nodes, thanks to its benefit in terms of carrier mobility and device threshold voltage tuning. We observe that it also opens a degree of freedom for device reliability optimization. By properly tuning the device gate stack, sufficiently reliable ultra-thin EOT devices with a 10 years lifetime at operating conditions are demonstrated. The extensive experimental datasets collected on a variety of processed 300mm wafers and presented here show the reliability improvement to be process - and architecture-independent and, as such, readily transferable to advanced device architectures as Tri-Gate (finFET) devices. We propose a physical model to understand the intrinsically superior reliability of the MOS system consisting of a Ge-based channel and a SiO2/HfO2 dielectric stack. The improved reliability properties here discussed strongly support (Si)Ge technology as a clear frontrunner for future CMOS technology nodes.

As the semiconductor industry approaches the limits of traditional silicon CMOS scaling, introduction of performance boosters like novel materials and innovative device structures has become necessary for the future of CMOS. High mobility materials are being considered to replace Si in the channel to achieve higher drive currents and switching speeds. Ge has particularly become of great interest as a channel material, owing to its high bulk hole and electron mobilities. However, replacement of Si channel by Ge requires several critical issues to be addressed in Ge MOS technology. High quality gate dielectric for surface passivation, low parasitic source/drain resistance and performance improvement in Ge NMOS are among the major challenges in realizing Ge CMOS. Detailed characterization of gate dielectric/channel interface and a deeper understanding of mobility degradation mechanisms are needed to address the Ge NMOS performance problem and to improve PMOS performance. In the first part of this dissertation, the electrical characterization results on Ge NMOS and PMOS devices fabricated with GeON gate dielectric are presented. Carrier scattering mechanisms are studied through low temperature mobility measurements. For the first time, the effect of substrate crystallographic orientation on inversion electron and hole mobilities is investigated. Direct formation of a high-k dielectric on Ge has not given good results in the past. A good quality interface layer is required before the deposition of a high-K dielectric. In the second part of this dissertation, ozone-oxidation process is introduced to engineer Ge/insulator interface. Electrical and structural characterizations and stability analysis are carried out and high quality Ge/dielectric interface with low interface trap density is demonstrated. Detailed extraction of interface trap density distribution across the bandgap and close to band edges of Ge, using low temperature conductance and capacitance measurements is presented. Ge N-MOSFETs have exhibited poor drive currents and low mobility, as reported by several different research groups worldwide. In spite of the increasing interest in Ge, the major mechanisms behind poor Ge NMOS performance have not been completely understood yet. In the last part of this dissertation, the results on Ge NMOS devices fabricated with the ozone-oxidation and the low temperature source/drain activation processes are discussed. These devices achieve the highest electron mobility to-date, about 1.5 times the universal Si mobility. Detailed interface characterizations, trapping analyses and gated Hall device measurements are performed to identify the mechanisms behind poor Ge NMOS performance in the past.

Since metal-oxide-semiconductor (MOS) device was first reported around 1959 and utilized for integrated circuits in 1961, complementary MOS technology has become the mainstream of semiconductor industry. Its performance has been improved based on scaling of dimensions of MOS field-effect-transistors (MOSFET) in accordance with Moore's law, which states that the density of MOSFETs due to scaling approximately doubles every two years. Entering into sub-100nm regime caused a lot of challenges. Traditional way of scaling no longer provided performance enhancement of individual MOSFETs. Increased channel doping which is required to prevent degradation of device electrostatics from short channel effects caused carrier mobility degradation. New inventions needed to be incorporated to sustain performance enhancement trend with scaling. Implementation of process induced strained Si technology allowed mobility enhancement, and high-K/metal gate instead of conventional poly-Si/SiO2 allowed continuing electrical gate oxide thickness scaling, hence extending the life span of Moore's law. As we are now moving toward 22nm logic technology and below, new concerns have been rapidly aroused. Controlling power consumption and performance variability are becoming as important as developing scaled devices with enhanced performance. Expandability of strained-Si channel technology via process induced strain also faces increasing complexity from ever tighter gate pitch and difficulties in controlling defect level with the channel stress enhancement techniques. At the same time, long-lasting planar MOSFET architecture also faces serious challenges due to the limits of controlling short channel effects. New paradigms and pathways for future technology seems to be required. As a result, new material sets, new device architectures and concepts are being vigorously explored in the literature. These new trends can be categorized into three groups: MOSFET structure with (non-Si) high mobility channel materials, advanced (non-planar) MOSFET structures, and MOSFET-type structures with new device operation concepts such as tunneling FETs. This dissertation presents research on high mobility channel MOSFET structures (planar and non-planar) using group IV material (mainly SiGe) for enhanced performance and reduced operating power. This work especially focuses on improving the performance of short channel device performance of SiGe channel pMOSFETs which has long been researched yet clearly demonstrated in literature only recently. To reach the goal, novel processing technologies such as millisecond flash source/drain anneal and high pressure hydrogen post-metal anneal are explored. Finally, performance dependence on channel and substrate direction has been analyzed to find the optimal use of these SiGe channels. This work describes an exciting opportunity of weighting the possibility of using high mobility channel MOSFETs for future logic technology.

This work presents research on high mobility channel MOSFET structures (planar and non-planar) using group IV material (mainly SiGe) for enhanced performance and reduced operating power. This work especially focuses on improving the performance of short channel device performance of SiGe channel pMOSFETs which has long been researched yet clearly demonstrated in literature only recently. To reach the goal, novel processing technologies such as millisecond flash source/drain anneal and high pressure hydrogen post-metal anneal are explored. Finally, performance dependence on channel and substrate direction has been analyzed to find the optimal use of these SiGe channels. This work describes an exciting opportunity of weighting the possibility of using high mobility channel MOSFETs for future logic technology.

The International Symposium for Testing and Failure Analysis (ISTFA) 2018 is co-located with the International Test Conference (ITC) 2018, October 28 to November 1, in Phoenix, Arizona, USA at the Phoenix Convention Center. The theme for the November 2018 conference is "Failures Worth Analyzing." While technology advances fast and the market demands the latest and the greatest, successful companies strive to stay competitive and remain profitable.

High Mobility Materials for CMOS Applications provides a comprehensive overview of recent developments in the field of (Si)Ge and III-V materials and their integration on Si. The book covers material growth and integration on Si, going all the way from device to circuit design. While the book's focus is on digital applications, a number of chapters also address the use of III-V for RF and analog applications, and in optoelectronics. With CMOS technology moving to the 10nm node and beyond, however, severe concerns with power dissipation and performance are arising, hence the need for this timely work on the advantages and challenges of the technology. Addresses each of the challenges of utilizing high mobility materials for CMOS applications, presenting possible solutions and the latest innovations Covers the latest advances in research on heterogeneous integration, gate stack, device design and scalability Provides a broad overview of the topic, from materials integration to circuits

Since the 90 nm CMOS technology node, geometric scaling of CMOS has been supplemented with strain to boost transistor drive current. Future CMOS technology nodes (i.e. beyond the 32 nm node) will require more significant changes to continue improvements in transistor performance. Novel CMOS channel materials and device architectures are one option for enhancing carrier transport and increasing device performance. In this work strained SiGe and Ge are examined as a means of increasing the drive current in deeply scaled CMOS. As part of this work a novel high mobility strained-Ge on-insulator substrate has been developed, and the hole transport characteristics of short channel and asymmetrically strained-SiGe channel p-MOSFETs have been explored. A thin-body biaxial compressive strained-Si/strained-Ge heterostructure on-insulator (HOI) substrate has been developed, which combines the electrostatic benefits of the thin-body architecture with the transport benefits of biaxial compressive strain. A novel Germanium on Silicon growth method and a low temperature bond and etch-back process have been developed to enable Ge HOI fabrication. P-MOSFETs were also fabricated using these substrates and the hole mobility characteristics were studied. The hole mobility and velocity characteristics of short channel biaxial compressive strained-Si 45 Geo. 55 p-MOSFETs on-insulator have also been examined. Devices with gate lengths down to 65 nm were fabricated. The short channel mobility characteristics were extracted and a 2.4x hole mobility enhancement relative to relaxed-Si was observed. The measured hole velocity enhancement is more modest at about 1.2x. Band structure and ballistic velocity simulations suggest that a more substantial velocity improvement can be expected with the incorporation of added longitudinal uniaxial compressive strain in the SiGe channel. The hole mobility characteristics of biaxial strained SiGe and Ge p-MOSFETs with applied uniaxial strain are also studied. The hole mobility in biaxial compressive strained SiGe is already enhanced relative to relaxed Si. It is observed that this mobility enhancement increases further with the application of 110 longitudinal uniaxial compressive strain. Since hole mobility and velocity are correlated through their dependence on the hole effective mass, a mass driven increase in mobility with applied uniaxial strain should result in an increase in velocity. Simulations have also been performed to estimate the hole effective mass change in asymmetric strained SiGe. Finally the piezo resistance coefficients of strained SiGe are extracted and found to be larger than in Si.