As feature dimensions of integrated circuits shrink, the associated geometrical constraints on junction depth impose severe restrictions on the thermal budget for processing such devices. Furthermore, due to the relatively low melting point of the first aluminum metallization level, such restrictions extend to the fabrication of multilevel structures that are now essential in increasing packing density of interconnect lines. The fabrication of ultra large scale integrated (ULSI) devices under thermal budget restrictions requires the reassessment of existing and the development of new microelectronic materials and processes. This book addresses three broad but interrelated areas. The first area focuses on the subject of rapid thermal processing (RTP), a technology that allows minimization of processing time while relaxing the constraints on high temperature. Initially developed to limit dopant redistribution, current applications of RTP are shown here to encompass annealing, oxidation, nitridation, silicidation, glass reflow, and contact sintering. In a second but complementary area, advances in equipment design and performance of rapid thermal processing equipment are presented in conjunction with associated issues of temperature measurement and control. Defect mechanisms are assessed together with the resulting properties of rapidly deposited and processed films. The concept of RTP integration for a full CMOS device process is also examined together with its impact on device characteristics.

P. Antognetti University of Genova, Italy Director of the NATO ASI The key importance of VLSI circuits is shown by the national efforts in this field taking place in several countries at differ ent levels (government agencies, private industries, defense de partments). As a result of the evolution of IC technology over the past two decades, component complexi ty has increased from one single to over 400,000 transistor functions per chip. Low cost of such single chip systems is only possible by reducing design cost per function and avoiding cost penalties for design errors. Therefore, computer simulation tools, at all levels of the design process, have become an absolute necessity and a cornerstone in the VLSI era, particularly as experimental investigations are very time-consuming, often too expensive and sometimes not at all feasible. As minimum device dimensions shrink, the need to understand the fabrication process in a quanti tati ve way becomes critical. Fine patterns, thin oxide layers, polycristalline silicon interco~ nections, shallow junctions and threshold implants, each become more sensitive to process variations. Each of these technologies changes toward finer structures requires increased understanding of the process physics. In addition, the tighter requirements for process control make it imperative that sensitivities be unde~ stood and that optimation be used to minimize the effect of sta tistical fluctuations.

The symposium provided a forum for reviewing and discussing all aspects of process integration, with special focus on nanoscaled technologies, 65 nm and beyond on DRAM, SRAM, flash memory, high density logic-low power, RF, mixed analog-digital, process integration yield, CMP chemistries, low-k processes, gate stacks, metal gates, rapid thermal processing, silicides, copper interconnects, carbon nanotubes, novel materials, high mobility substrates (SOI, sSi, SiGe, GeOI), strain engineering, and hybrid integration.