As the complexity of modern embedded systems increases, it becomes less practical to design monolithic processing platforms. As a result, reconfigurable computing is being adopted widely for more flexible design. Reconfigurable Computers offer the spatial parallelism and fine-grained customizability of application-specific circuits with the postfabrication programmability of software. To make the most of this unique combination of performance and flexibility, designers need to be aware of both hardware and software issues. FPGA users must think not only about the gates needed to perform a computation but also about the software flow that supports the design process. The goal of this book is to help designers become comfortable with these issues, and thus be able to exploit the vast opportunities possible with reconfigurable logic.

This title serves as an introduction ans reference for the field, with the papers that have shaped the hardware/software co-design since its inception in the early 90s.

Application hardware-software co-design for reconfigurable computing systems.

Rapid energy estimation for energy efficient applications using field-programmable gate arrays (FPGAs) remains a challenging research topic. Energy dissipation and efficiency have prevented the widespread use of FPGA devices in embedded systems, where energy efficiency is a key performance metric. Helping overcome these challenges, Energy Efficient

This thesis describes a tool that helps in analyzing the current execution state in the processing elements on a reconfigurable co-processor and facilitates an integrated HW/SW debug environment. The described tool has most of the functionality of a traditional hardware simulator and it executes faster than the simulator. This tool exploits the readback capabilities of Xilinx FPGA, through which the state of execution is extracted and is sent back to the general-purpose processor. This allows the user to identify problems in hardware logic for static and dynamic reconfiguration, since this tool is invoked from a software application running in debugged mode, the user has the ability to observe and control the hardware and software design simultaneously. This tool also helps in accelerating the hardware debugging by letting the design run on hardware till the user determined point of interest and then forcing the state of design into the hardware simulator for functional or timing simulation. Software debugging, which is well established, involves setting break points to halt the software upon execution of specific routines and line numbers, observing data structures, viewing the call stack and setting up watch-conditions. Hardware debugging includes monitoring the state of execution in the FPGA and determining co-processor board RAM and FIFO contents. In this thesis, an integrated hardware execution and simulation environment is presented to the user, providing many of the features found in a standard hardware simulator such as watch-points, clock stepping and signal probing. Hardware watch-points allows the hardware design to stop execution whenever a user-defined trigger condition is reached. This tool allows the user to step a user-defined number of clock cycles enabling easy recreation of the problem in hardware. Different approaches for adding watch-point logic into the design are presented, with the goal of minimizing the area overhead without affecting timing (maximum frequency) or the place and route time for the overall circuit. Providing flexibility to the user to support changing of watch-point conditions is an additional requirement. Automating watch-point logic identification in a placed and routed design and thus automating the change in its value is also described.

Reconfigurable computing techniques and adaptive systems are some of the most promising architectures for microprocessors. Reconfigurable and Adaptive Computing: Theory and Applications explores the latest research activities on hardware architecture for reconfigurable and adaptive computing systems. The first section of the book covers reconfigurable systems. The book presents a software and hardware codesign flow for coarse-grained systems-on-chip, a video watermarking algorithm for the H.264 standard, a solution for regular expressions matching systems, and a novel field programmable gate array (FPGA)-based acceleration solution with MapReduce framework on multiple hardware accelerators. The second section discusses network-on-chip, including an implementation of a multiprocessor system-on-chip platform with shared memory access, end-to-end quality-of-service metrics modeling based on a multi-application environment in network-on-chip, and a 3D ant colony routing (3D-ACR) for network-on-chip with three different 3D topologies. The final section addresses the methodology of system codesign. The book introduces a new software–hardware codesign flow for embedded systems that models both processors and intellectual property cores as services. It also proposes an efficient algorithm for dependent task software–hardware codesign with the greedy partitioning and insert scheduling method (GPISM) by task graph.