Principles of VLSI RTL Design
Title | Principles of VLSI RTL Design PDF eBook |
Author | Sanjay Churiwala |
Publisher | Springer |
Pages | 182 |
Release | 2011-05-12 |
Genre | Technology & Engineering |
ISBN | 9781441992956 |
Since register transfer level (RTL) design is less about being a bright engineer, and more about knowing the downstream implications of your work, this book explains the impact of design decisions taken that may give rise later in the product lifecycle to issues related to testability, data synchronization across clock domains, synthesizability, power consumption, routability, etc., all which are a function of the way the RTL was originally written. Readers will benefit from a highly practical approach to the fundamentals of these topics, and will be given clear guidance regarding necessary safeguards to observe during RTL design.
Principles of VLSI RTL Design
Title | Principles of VLSI RTL Design PDF eBook |
Author | Sanjay Churiwala |
Publisher | Springer Science & Business Media |
Pages | 192 |
Release | 2011-05-04 |
Genre | Technology & Engineering |
ISBN | 1441992960 |
Since register transfer level (RTL) design is less about being a bright engineer, and more about knowing the downstream implications of your work, this book explains the impact of design decisions taken that may give rise later in the product lifecycle to issues related to testability, data synchronization across clock domains, synthesizability, power consumption, routability, etc., all which are a function of the way the RTL was originally written. Readers will benefit from a highly practical approach to the fundamentals of these topics, and will be given clear guidance regarding necessary safeguards to observe during RTL design.
Principles of VLSI Rtl Design
Title | Principles of VLSI Rtl Design PDF eBook |
Author | Sanjay Churiwala |
Publisher | |
Pages | 200 |
Release | 2011-05-06 |
Genre | |
ISBN | 9781441992970 |
Principles of Verifiable RTL Design
Title | Principles of Verifiable RTL Design PDF eBook |
Author | Lionel Bening |
Publisher | Springer Science & Business Media |
Pages | 297 |
Release | 2001-05-31 |
Genre | Computers |
ISBN | 0792373685 |
The first edition of Principles of Verifiable RTL Design offered a common sense method for simplifying and unifying assertion specification by creating a set of predefined specification modules that could be instantiated within the designer's RTL. Since the release of the first edition, an entire industry-wide initiative for assertion specification has emerged based on ideas presented in the first edition. This initiative, known as the Open Verification Library Initiative (www.verificationlib.org), provides an assertion interface standard that enables the design engineer to capture many interesting properties of the design and precludes the need to introduce new HDL constructs (i.e., extensions to Verilog are not required). Furthermore, this standard enables the design engineer to `specify once,' then target the same RTL assertion specification over multiple verification processes, such as traditional simulation, semi-formal and formal verification tools. The Open Verification Library Initiative is an empowering technology that will benefit design and verification engineers while providing unity to the EDA community (e.g., providers of testbench generation tools, traditional simulators, commercial assertion checking support tools, symbolic simulation, and semi-formal and formal verification tools). The second edition of Principles of Verifiable RTL Design expands the discussion of assertion specification by including a new chapter entitled `Coverage, Events and Assertions'. All assertions exampled are aligned with the Open Verification Library Initiative proposed standard. Furthermore, the second edition provides expanded discussions on the following topics: start-up verification; the place for 4-state simulation; race conditions; RTL-style-synthesizable RTL (unambiguous mapping to gates); more `bad stuff'. The goal of the second edition is to keep the topic current. Principles of Verifiable RTL Design, A Functional Coding Style Supporting Verification Processes, Second Edition tells you how you can write Verilog to describe chip designs at the RTL level in a manner that cooperates with verification processes. This cooperation can return an order of magnitude improvement in performance and capacity from tools such as simulation and equivalence checkers. It reduces the labor costs of coverage and formal model checking by facilitating communication between the design engineer and the verification engineer. It also orients the RTL style to provide more useful results from the overall verification process.
Principles of Verifiable RTL Design
Title | Principles of Verifiable RTL Design PDF eBook |
Author | Lionel Bening |
Publisher | Springer Science & Business Media |
Pages | 266 |
Release | 2007-05-08 |
Genre | Technology & Engineering |
ISBN | 0306470160 |
Principles of Verifiable RTL Design: A Functional Coding Style Supporting Verification Processes in Verilog explains how you can write Verilog to describe chip designs at the RT-level in a manner that cooperates with verification processes. This cooperation can return an order of magnitude improvement in performance and capacity from tools such as simulation and equivalence checkers. It reduces the labor costs of coverage and formal model checking by facilitating communication between the design engineer and the verification engineer. It also orients the RTL style to provide more useful results from the overall verification process. The intended audience for Principles of Verifiable RTL Design: A Functional Coding Style Supporting Verification Processes in Verilog is engineers and students who need an introduction to various design verification processes and a supporting functional Verilog RTL coding style. A second intended audience is engineers who have been through introductory training in Verilog and now want to develop good RTL writing practices for verification. A third audience is Verilog language instructors who are using a general text on Verilog as the course textbook but want to enrich their lectures with an emphasis on verification. A fourth audience is engineers with substantial Verilog experience who want to improve their Verilog practice to work better with RTL Verilog verification tools. A fifth audience is design consultants searching for proven verification-centric methodologies. A sixth audience is EDA verification tool implementers who want some suggestions about a minimal Verilog verification subset. Principles of Verifiable RTL Design: A Functional Coding Style Supporting Verification Processes in Verilog is based on the reality that comes from actual large-scale product design process and tool experience.
Principles of Verifiable Rtl Design
Title | Principles of Verifiable Rtl Design PDF eBook |
Author | Lionel Bening |
Publisher | |
Pages | 308 |
Release | 2014-09-01 |
Genre | |
ISBN | 9781475774177 |
VLSI Test Principles and Architectures
Title | VLSI Test Principles and Architectures PDF eBook |
Author | Laung-Terng Wang |
Publisher | Elsevier |
Pages | 809 |
Release | 2006-08-14 |
Genre | Technology & Engineering |
ISBN | 0080474799 |
This book is a comprehensive guide to new DFT methods that will show the readers how to design a testable and quality product, drive down test cost, improve product quality and yield, and speed up time-to-market and time-to-volume. - Most up-to-date coverage of design for testability. - Coverage of industry practices commonly found in commercial DFT tools but not discussed in other books. - Numerous, practical examples in each chapter illustrating basic VLSI test principles and DFT architectures.