CMOS DC-DC Converters aims to provide a comprehensive dissertation on the matter of monolithic inductive Direct-Current to Direct-Current (DC-DC) converters. For this purpose seven chapters are defined which will allow the designer to gain specific knowledge on the design and implementation of monolithic inductive DC-DC converters, starting from the very basics.

Ultimate integration of power switch-mode converter relies on two research paths. One path experiments the development of switched-capacitor converters. This approach fits silicon integration but is still limited in term of power density. Inductive DC-DC architectures of converters suffer by the values and size of passive components. This limitation is addressed with an increase in frequency. Increase in switching losses in switches leads to consider advanced technological nodes. Consequently, the capability with respect to input voltage is then limited. Handling 3.3 V input voltage to deliver an output voltage in the range 0.6 V to 1.2 V appears a challenging specification for an inductive buck converter if the smallest footprint is targeted at +90 % efficiency. Smallest footprint is approached through a 3D assembly of passive components to the active silicon die. High switching frequency is also considered to shrink the values of passive components as much as possible. In the context of on-chip power supply, the silicon technology is dictated by the digital functions. Complementary Metal-Oxide- Semiconductor (CMOS) bulk C40 is selected as a study case for 3.3 V input voltage. 3.3 V Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) features poor figure of merits and 1.2 V standard core, regular devices are preferred. Moreover future integration as an on-chip power supply is more compatible. A three-MOSFET cascode arrangement is experimented and confronted experimentally to a standard buck arrangement in the same technology. The coupled-phase architecture enables to reduce the switching frequency to half the operating frequency of the passive devices. +100MHz is selected for operation of passive devices. CMOS bulk C40 offers Metal-Oxide-Metal (MOM) and MOS capacitors, in density too low to address the decoupling requirements. Capacitors have to be added externally to the silicon die but in a tight combination. Trench-cap technology is selected and capacitors are fabricated on a separate die that will act as an interposer to receive the silicon die as well as the inductors. The work delivers an object containing a one-phase buck converter with the silicon die flip-chipped on a capacitor interposer where a tiny inductor die is reported. The one-phase demonstrator is suitable for coupled-phase demonstration. Standard and cascode configurations are experimentally compared at 100 MHz and 200 MHz switching frequency. A design methodology is presented to cover a system-to-device approach. The active silicon die is the central design part as the capacitive interposer is fabricated by IPDiA and inductors are provided by Tyndall National Institute. The assembly of the converter sub-parts is achieved using an industrial process. The work details a large set of measurements to show the performances of the delivered DC/DC converters as well as its limitations. A 91.5% peak efficiency at 100MHz switching frequency has been demonstrated.

This book provides a comprehensive, single-source on resonant switched-capacitor converters. It is written in the style of a handbook, with systematic guidelines, and includes implementation examples. The authors explore integrated hybrid resonant DCDC converters in order to achieve highly compact, energy efficient and cost-effective power management solutions in the growing fields of wearables and internet-of-things applications. They provide an introduction into hybrid converters as a new and promising converter class, which merges capacitive and inductive conversion concepts into one. Coverage ranges from fundamentals to implementation details, including topics such as power stage design, gate drive schemes, different control mechanisms for resonant operation and integrated passives. Introduces a new, multi-ratio resonant converter architecture, which enables lower switching frequencies and better passive component utilization; Discusses circuit block design for high efficiency of the power stage; Explores implementation details and concepts for integrated passives; Derives models, implements and compares to each other different control mechanisms.

Bachelor Thesis from the year 2013 in the subject Electrotechnology, grade: Bachelor, Harbin Engineering University (College of Automation), course: Electronics, language: English, abstract: In recent years, with the development of power electronic devices control theory and the increasing demand of high-quality power supply, power electronics technology has aroused widely attention from scholars. DC-DC power converters are employed in a variety of applications, including power supplies for personal computers, office equipment; spacecraft power systems, laptop, Cell phones, and telecommunications equipment, as well as dc motor drives. In this project a detailed study of zero current switching buck converters is done and also practically implemented in hardware. In addition a mathematical analysis of switching loss occurring in MOSFET's is also presented and a short study of zero voltage switching is also appended. During the hardware implementation the Ton, Toff and operating frequency were found out and thoroughly tuned through the IC555 circuit and various waveforms across inductors, capacitors, load resistor and test points were noted down. In this thesis, the Buck type circuit structure and working principle are analyzed and a DC-DC buck converter is designed. The designed converter uses ZCS scheme and realized the function that the power form is converted from 12V DC voltages to 5 V DC voltages. The output voltage can be adjusted according to the output resistor. The output voltage is stable and the performance of the designed converter is ensured. Simulation study was carried out and effectiveness of the designed converter is verified by simulation results. Finlay design is implemented in hardware and PCB layout as well.

Power consumption becomes the most important design goal in a wide range of electronic systems. There are two driving forces towards this trend: continuing device scaling and ever increasing demand of higher computing power. First, device scaling continues to satisfy Moore’s law via a conventional way of scaling (More Moore) and a new way of exploiting the vertical integration (More than Moore). Second, mobile and IT convergence requires more computing power on the silicon chip than ever. Cell phones are now evolving towards mobile PC. PCs and data centers are becoming commodities in house and a must in industry. Both supply enabled by device scaling and demand triggered by the convergence trend realize more computation on chip (via multi-core, integration of diverse functionalities on mobile SoCs, etc.) and finally more power consumption incurring power-related issues and constraints. Energy-Aware System Design: Algorithms and Architectures provides state-of-the-art ideas for low power design methods from circuit, architecture to software level and offers design case studies in three fast growing areas of mobile storage, biomedical and security. Important topics and features: - Describes very recent advanced issues and methods for energy-aware design at each design level from circuit and architecture to algorithm level, and also covering important blocks including low power main memory subsystem and on-chip network at architecture level - Explains efficient power conversion and delivery which is becoming important as heterogeneous power sources are adopted for digital and non-digital parts - Investigates 3D die stacking emphasizing temperature awareness for better perspective on energy efficiency - Presents three practical energy-aware design case studies; novel storage device (e.g., solid state disk), biomedical electronics (e.g., cochlear and retina implants), and wireless surveillance camera systems. Researchers and engineers in the field of hardware and software design will find this book an excellent starting point to catch up with the state-of-the-art ideas of low power design.