The third Conference on Mathematical Models and Numerical Simulation in Electronic Industry brought together researchers in mathematics, electrical engineering and scientists working in industry. The contributions to this volume try to bridge the gap between basic and applied mathematics, research in electrical engineering and the needs of industry.

This book constitutes the refereed proceedings of the 13th International Workshop on Power and Timing Modeling, Optimization and Simulation, PATMOS 2003, held in Torino, Italy in September 2003. The 43 revised full papers and 18 revised poster papers presented together with three keynote contributions were carefully reviewed and selected from 85 submissions. The papers are organized in topical sections on gate-level modeling and characterization, interconnect modeling and optimization, asynchronous techniques, RTL power modeling and memory optimization, high-level modeling, power-efficient technologies and designs, communication modeling and design, and low-power issues in processors and multimedia.

Circuit simulation has become an essential tool in circuit design and without it's aid, analogue and mixed-signal IC design would be impossible. However the applicability and limitations of circuit simulators have not been generally well understood and this book now provides a clear and easy to follow explanation of their function. The material covered includes the algorithms used in circuit simulation and the numerical techniques needed for linear and non-linear DC analysis, transient analysis and AC analysis. The book goes on to explain the numeric methods to include sensitivity and tolerance analysis and optimisation of component values for circuit design. The final part deals with logic simulation and mixed-signal simulation algorithms. There are comprehensive and detailed descriptions of the numerical methods and the material is presented in a way that provides for the needs of both experienced engineers who wish to extend their knowledge of current tools and techniques, and of advanced students and researchers who wish to develop new simulators.

In November 2001 the Mathematical Research Center at Oberwolfach, Germany, hosted the third Conference on Mathematical Models and Numerical Simulation in Electronic Industry. It brought together researchers in mathematics, electrical engineering and scientists working in industry.The contributions to this volume try to bridge the gap between basic and applied mathematics, research in electrical engineering and the needs of industry.

As MOS devices are scaled to meet increasingly demanding circuit specifications, process variations have a greater effect on the reliability of circuit performance. For this reason, statistical techniques are required to design integrated circuits with maximum yield. Statistical Modeling for Computer-Aided Design of MOS VLSI Circuits describes a statistical circuit simulation and optimization environment for VLSI circuit designers. The first step toward accomplishing statistical circuit design and optimization is the development of an accurate CAD tool capable of performing statistical simulation. This tool must be based on a statistical model which comprehends the effect of device and circuit characteristics, such as device size, bias, and circuit layout, which are under the control of the circuit designer on the variability of circuit performance. The distinctive feature of the CAD tool described in this book is its ability to accurately model and simulate the effect in both intra- and inter-die process variability on analog/digital circuits, accounting for the effects of the aforementioned device and circuit characteristics. Statistical Modeling for Computer-Aided Design of MOS VLSI Circuits serves as an excellent reference for those working in the field, and may be used as the text for an advanced course on the subject.

Analog circuit design is often the bottleneck when designing mixed analog-digital systems. A Top-Down, Constraint-Driven Design Methodology for Analog Integrated Circuits presents a new methodology based on a top-down, constraint-driven design paradigm that provides a solution to this problem. This methodology has two principal advantages: (1) it provides a high probability for the first silicon which meets all specifications, and (2) it shortens the design cycle. A Top-Down, Constraint-Driven Design Methodology for Analog Integrated Circuits is part of an ongoing research effort at the University of California at Berkeley in the Electrical Engineering and Computer Sciences Department. Many faculty and students, past and present, are working on this design methodology and its supporting tools. The principal goals are: (1) developing the design methodology, (2) developing and applying new tools, and (3) `proving' the methodology by undertaking `industrial strength' design examples. The work presented here is neither a beginning nor an end in the development of a complete top-down, constraint-driven design methodology, but rather a step in its development. This work is divided into three parts. Chapter 2 presents the design methodology along with foundation material. Chapters 3-8 describe supporting concepts for the methodology, from behavioral simulation and modeling to circuit module generators. Finally, Chapters 9-11 illustrate the methodology in detail by presenting the entire design cycle through three large-scale examples. These include the design of a current source D/A converter, a Sigma-Delta A/D converter, and a video driver system. Chapter 12 presents conclusions and current research topics. A Top-Down, Constraint-Driven Design Methodology for Analog Integrated Circuits will be of interest to analog and mixed-signal designers as well as CAD tool developers.

This book constitutes the refereed proceedings of the 22nd International Conference on Integrated Circuit and System Design, PATMOS 2012, held in Newcastle, UK Spain, in September 2012. The 25 revised full papers presented were carefully reviewed and selected from numerous submissions. The paper feature emerging challenges in methodologies and tools for the design of upcoming generations of integrated circuits and systems, including reconfigurable hardware such as FPGAs. The technical program focus on timing, performance and power consumption as well as architectural aspects with particular emphasis on modeling, design, characterization, analysis and optimization.