Advancements in very large scale integration (VLSI) technology have led to unprecedented transistor and interconnect scaling. Further miniaturization by traditional IC scaling in future planar CMOS technology faces significant challenges. Stacking of ICs (3D IC) using three dimensional (3D) integration technology helps in significantly reducing wiring lengths, interconnect latency and power dissipation while reducing the size of the chip and enhancing performance. Interposer technology with ultra-fine pitch interconnections needs to be developed to support the huge I/O connection requirement for packaging 3D ICs. Through vias in stacked silicon ICs and interposers are the key components of a 3D system.

3D Integration is being touted as the next semiconductor revolution. This book provides a comprehensive coverage on the design and modeling aspects of 3D integration, in particularly, focus on its electrical behavior. Looking from the perspective the Silicon Via (TSV) and Glass Via (TGV) technology, the book introduces 3DICs and Interposers as a technology, and presents its application in numerical modeling, signal integrity, power integrity and thermal integrity. The authors underscored the potential of this technology in design exchange formats and power distribution.

Emerging I/O density and bandwidth requirements are driving packages to low-CTE silicon, glass and organic substrates for higher wiring density and reliability of interconnections and Cu-low k dielectrics. These are needed for high performance applications as 2.5D packages in large-size, and also as ultra-thin packages for consumer applications that are directly assembled on the board without the need for an intermediate package. The trend to low-CTE packages (CTE of 3-8ppm/°C), however, creates large CTE mismatch with the board on which they are assembled. Interconnection reliability is, therefore, a major concern when low CTE interposers are surface mounted onto organic system boards via solder joints. This reliability concern is further aggravated with large package sizes and finer pitch. For wide acceptance of low CTE packages in high volume production, it is also critical to assemble them on board using standard Surface Mount Technologies (SMT) without the need for under-fill. This research aims to demonstrate reliable 400 micron pitch solder interconnections from low CTE glass interposers directly assembled onto organic boards by overcoming the above challenges using two approaches; 1) Stress-relief dielectric build up layers on the back of the interposer, 2) Polymer collar around the solder bumps for shear stress re-distribution. A comprehensive methodology based on modeling, design, test vehicle fabrication and characterization is employed to study and demonstrate the efficacy of these approaches in meeting the interposer-to-board interconnection requirements. The effect of varying geometrical and material properties of both build-up layers and polymer collar is studied through Finite Element Modeling. Interposers were designed and fabricated with the proposed approaches to demonstrate process feasibility.

3D Integration is being touted as the next semiconductor revolution. This book provides a comprehensive coverage on the design and modeling aspects of 3D integration, in particularly, focus on its electrical behavior. Looking from the perspective the Silicon Via (TSV) and Glass Via (TGV) technology, the book introduces 3DICs and Interposers as a technology, and presents its application in numerical modeling, signal integrity, power integrity and thermal integrity. The authors underscored the potential of this technology in design exchange formats and power distribution.

Modeling and Design of Electromagnetic Compatibility for High-Speed Printed Circuit Boards and Packaging presents the electromagnetic modelling and design of three major electromagnetic compatibility (EMC) issues related to the high-speed printed circuit board (PCB) and electronic packages: signal integrity (SI), power integrity (PI), and electromagnetic interference (EMI). The emphasis is put on two essential passive components of PCBs and packages: the power distribution network and the signal distribution network. This book includes two parts. Part one talks about the field-circuit hybrid methods used for the EMC modeling, including the modal method, the integral equation method, the cylindrical wave expansion method and the de-embedding method. Part two illustrates EMC design methods and explores the applications of novel metamaterials and two-dimensional materials on traditional EMC problems. This book is designed to enhance worthwhile electromagnetic theory and mathematical methods for practical engineers and to train students with advanced EMC applications.

This book constitutes the proceedings of the 26th International Symposium on VLSI Design and Test, VDAT 2022, which took place in Jammu, India, in July 2022. The 32 regular papers and 16 short papers presented in this volume were carefully reviewed and selected from 220 submissions. They were organized in topical sections as follows: Devices and Technology; Sensors; Analog/Mixed Signal; Digital Design; Emerging Technologies and Memory; System Design.