The scaling of device dimensions with a simultaneous increase in functional density has imposed tremendous challenges for materials, technology, integration and reliability of interconnects. To meet requirements of the ITRS roadmap, new materials are being introduced at a faster pace in all functions of multilevel interconnects. The issues addressed in this book cannot be dispelled as simply selecting a low-k material and integrating it into a copper damascene process. The intricacies of the back end for sub-100nm technology include novel processing of low-k materials, employing pore-sealing techniques and capping layers, introducing advanced dielectric and diffusion barriers, and developing novel integration schemes. This is in addition to concerns of performance, yield, and reliability appropriate to nanoscaled interconnects. Although many challenges continue to impede progress along the ITRS roadmap, the contributions in this book confront them head-on. It provides a scientific understanding of the issues and stimulate new approaches to advanced multilevel interconnects.

Since overall circuit performance has depended primarily on transistor properties, previous efforts to enhance circuit and system speed were focused on transistors as well. During the last decade, however, the parasitic resistance, capacitance, and inductance associated with interconnections began to influence circuit performance and will be the primary factors in the evolution of nanoscale ULSI technology. Because metallic conductivity and resistance to electromigration of bulk copper (Cu) are better than aluminum, use of copper and low-k materials is now prevalent in the international microelectronics industry. As the feature size of the Cu-lines forming interconnects is scaled, resistivity of the lines increases. At the same time electromigration and stress-induced voids due to increased current density become significant reliability issues. Although copper/low-k technology has become fairly mature, there is no single book available on the promise and challenges of these next-generation technologies. In this book, a leader in the field describes advanced laser systems with lower radiation wavelengths, photolithography materials, and mathematical modeling approaches to address the challenges of Cu-interconnect technology.

Finding new materials for copper/low-k interconnects is critical to the continuing development of computer chips. While copper/low-k interconnects have served well, allowing for the creation of Ultra Large Scale Integration (ULSI) devices which combine over a billion transistors onto a single chip, the increased resistance and RC-delay at the smaller scale has become a significant factor affecting chip performance. Advanced Interconnects for ULSI Technology is dedicated to the materials and methods which might be suitable replacements. It covers a broad range of topics, from physical principles to design, fabrication, characterization, and application of new materials for nano-interconnects, and discusses: Interconnect functions, characterisations, electrical properties and wiring requirements Low-k materials: fundamentals, advances and mechanical properties Conductive layers and barriers Integration and reliability including mechanical reliability, electromigration and electrical breakdown New approaches including 3D, optical, wireless interchip, and carbon-based interconnects Intended for postgraduate students and researchers, in academia and industry, this book provides a critical overview of the enabling technology at the heart of the future development of computer chips.