Low Power UWB CMOS Radar Sensors deals with the problem of designing low cost CMOS radar sensors. The radar sensor uses UWB signals in order to obtain a reasonable target separation capability, while maintaining a maximum signal frequency below 2 GHz. This maximum frequency value is well within the reach of current CMOS technologies. The use of UWB signals means that most of the methodologies used in the design of circuits and systems that process narrow band signals, can no longer be applied. Low Power UWB CMOS Radar Sensors provides an analysis between the interaction of UWB signals, the antennas and the processing circuits. This analysis leads to some interesting conclusions on the types of antennas and types of circuits that should be used. A methodology to compare the noise performance of UWB processing circuits is also derived. This methodology is used to analyze and design the constituting circuits of the radar transceiver. In order to validate the design methodology a CMOS prototype is designed and experimentally evaluated.

Low Power UWB CMOS Radar Sensors deals with the problem of designing low cost CMOS radar sensors. The radar sensor uses UWB signals in order to obtain a reasonable target separation capability, while maintaining a maximum signal frequency below 2 GHz. This maximum frequency value is well within the reach of current CMOS technologies. The use of UWB signals means that most of the methodologies used in the design of circuits and systems that process narrow band signals, can no longer be applied. Low Power UWB CMOS Radar Sensors provides an analysis between the interaction of UWB signals, the antennas and the processing circuits. This analysis leads to some interesting conclusions on the types of antennas and types of circuits that should be used. A methodology to compare the noise performance of UWB processing circuits is also derived. This methodology is used to analyze and design the constituting circuits of the radar transceiver. In order to validate the design methodology a CMOS prototype is designed and experimentally evaluated.

Low-Power High-Speed ADCs for Nanometer CMOS Integration is about the design and implementation of ADC in nanometer CMOS processes that achieve lower power consumption for a given speed and resolution than previous designs, through architectural and circuit innovations that take advantage of unique features of nanometer CMOS processes. A phase lock loop (PLL) clock multiplier has also been designed using new circuit techniques and successfully tested. 1) A 1.2V, 52mW, 210MS/s 10-bit two-step ADC in 130nm CMOS occupying 0.38mm2. Using offset canceling comparators and capacitor networks implemented with small value interconnect capacitors to replace resistor ladder/multiplexer in conventional sub-ranging ADCs, it achieves 74dB SFDR for 10MHz and 71dB SFDR for 100MHz input. 2) A 32mW, 1.25GS/s 6-bit ADC with 2.5GHz internal clock in 130nm CMOS. A new type of architecture that combines flash and SAR enables the lowest power consumption, 6-bit >1GS/s ADC reported to date. This design can be a drop-in replacement for existing flash ADCs since it does require any post-processing or calibration step and has the same latency as flash. 3) A 0.4ps-rms-jitter (integrated from 3kHz to 300MHz offset for >2.5GHz) 1-3GHz tunable, phase-noise programmable clock-multiplier PLL for generating sampling clock to the SAR ADC. A new loop filter structure enables phase error preamplification to lower PLL in-band noise without increasing loop filter capacitor size.

Ranging from the theoretical basis of UWB sensors via implementation issues to applications, this much-needed book bridges the gap between designers and appliers working in civil engineering, biotechnology, medical engineering, robotic, mechanical engineering, safety and homeland security. From the contents: * History * Signal and systems in time and frequency domain * Propagation of electromagnetic waves (in frequency and time domain) * UWB-Principles * UWB-antennas and applicators * Data processing * Applications

Omnidirectional Inductive Powering for Biomedical Implants investigates the feasibility of inductive powering for capsule endoscopy and freely moving systems in general. The main challenge is the random position and orientation of the power receiving system with respect to the emitting magnetic field. Where classic inductive powering assumes a predictable or fixed alignment of the respective coils, the remote system is now free to adopt just any orientation while still maintaining full power capabilities. Before elaborating on different approaches towards omnidirectional powering, the design and optimisation of a general inductive power link is discussed in all its aspects. Special attention is paid to the interaction of the inductive power link with the patient’s body. Putting theory into practice, the implementation of an inductive power link for a capsule endoscope is included in a separate chapter.

Structured Analog CMOS Design describes a structured analog design approach that makes it possible to simplify complex analog design problems and develop a design strategy that can be used for the design of large number of analog cells. It intentionally avoids treating the analog design as a mathematical problem, developing a design procedure based on the understanding of device physics and approximations that give insight into parameter interdependences. The basic design concept consists in analog cell partitioning into the basic analog structures and sizing of these basic analog structures in a predefined procedural design sequence. The procedural design sequence ensures the correct propagation of design specifications, the verification of parameter limits and the local optimization loops. The proposed design procedure is also implemented as a CAD tool that follows this book.