This work covers the design of CMOS fully integrated low power low phase noise voltage controlled oscillators for telecommunication or datacommuni- tion systems. The need for low power is obvious, as mobile wireless telecommunications are battery operated. As wireless telecommunication systems use oscillators in frequency synthesizers for frequency translation, the selectivity and signal to noise ratio of receivers and transmitters depend heavily on the low phase noise performance of the implemented oscillators. Datacommunication s- tems need low jitter, the time-domain equivalent of low phase noise, clocks for data detection and recovery. The power consumption is less critical. The need for multi-band and multi-mode systems pushes the high-integration of telecommunication systems. This is o?ered by sub-micron CMOS feat- ing digital ?exibility. The recent crisis in telecommunication clearly shows that mobile hand-sets became mass-market high-volume consumer products, where low-cost is of prime importance. This need for low-cost products - livens tremendously research towards CMOS alternatives for the bipolar or BiCMOS solutions in use today.

CMOS PLLs and VCOs for 4G Wireless is the first book devoted to the subject of CMOS PLL and VCO design for future broadband 4th generation wireless devices. These devices will be handheld-centric, requiring very low power consumption and small footprint. They will be able to work across multiple bands and multiple standards covering WWAN (GSM,WCDMA) ,WLAN(802.11 a/b/g) and WPAN(Bluetooth) with different modulations, channel bandwidths , phase noise requirements ,etc. As such, this book discusses design, modeling and optimization techniques for low power fully integrated broadband PLLs and VCOs in deep submicron CMOS. First, the PLL and VCO performances are studied in the context of the chosen multi-band multi-standard, radio architecture and the adopted frequency plan. Next a thorough study of the design requirements for broadband PLL/VCO design is conducted together with modeling techniques for noise sources in a PLL and VCO focusing on optimization of integrated phase noise for multi-carrier OFDM 64-QAM type applications. Design examples for multi-standard 802.111a/b/g as well as for GSM/WCDMA are fully described and experimental results from 0.18 micron CMOS test chips have demonstrated the validity of the proposed design and optimization techniques. Equally important the work describes techniques for robust high volume production of RF radios in general and for integrated PLL/VCO design in particular including issues such as supply sensitivity, ground bounce and calibration mechanisms. CMOS PLLS and VCOs for 4G Wireless will be of interest to graduate students in electrical and computer engineering, design managers and RFIC designers in wireless semiconductor companies.

Low Power Consumption is one of the critical issues in the performance of small battery-powered handheld devices. Mobile terminals feature an ever increasing number of wireless communication alternatives including GPS, Bluetooth, GSM, 3G, WiFi or DVB-H. Considering that the total power available for each terminal is limited by the relatively slow increase in battery performance expected in the near future, the need for efficient circuits is now critical. This book presents the basic techniques available to design low power RF CMOS analogue circuits. It gives circuit designers a complete guide of alternatives to optimize power consumption and explains the application of these rules in the most common RF building blocks: LNA, mixers and PLLs. It is set out using practical examples and offers a unique perspective as it targets designers working within the standard CMOS process and all the limitations inherent in these technologies.

Design of High-Performance CMOS Voltage-Controlled Oscillators presents a phase noise modeling framework for CMOS ring oscillators. The analysis considers both linear and nonlinear operation. It indicates that fast rail-to-rail switching has to be achieved to minimize phase noise. Additionally, in conventional design the flicker noise in the bias circuit can potentially dominate the phase noise at low offset frequencies. Therefore, for narrow bandwidth PLLs, noise up conversion for the bias circuits should be minimized. We define the effective Q factor (Qeff) for ring oscillators and predict its increase for CMOS processes with smaller feature sizes. Our phase noise analysis is validated via simulation and measurement results. The digital switching noise coupled through the power supply and substrate is usually the dominant source of clock jitter. Improving the supply and substrate noise immunity of a PLL is a challenging job in hostile environments such as a microprocessor chip where millions of digital gates are present.

In an era dominated by the highly demanding wireless communication system, there is a great need for developing small, cheap, and low power RF sub-systems. This demand has lead to significant research on completely integrated transceiver systems. One of the great challenges in an integrated transceiver system is the frequency synthesizer. Frequency synthesizers are usually implemented using a phase locked loop (PLL) and low frequency highly stable crystal oscillator. The spectral purity of a synthesized carrier signal depends on the kind of Voltage Controlled Oscillator (VCO) used. Hence successful implementation of a low phase noise, completely integrated VCO in standard CMOS process is a major step towards implementing a completely integrated transceiver. The best VCO architecture in terms of noise performance is LC-VCO. The aim of the current research is to design a completely integrated 1.8 GHz LC-VCO for a GSM or DCS-1800 receiver in standard CMOS 0.35 [mu]m technology. The major challenge in a completely integrated LC-VCO is to develop an fully integrated inductor. In this research various means of implementing an integrated inductor have been scrutinized and the best feasible among them the on-chip spiral inductor has been analyzed elaborately. The complete design cycle from describing the specification of an inductor to the final layout in Cadence has been described. Also a new symmetrical, highly balanced on-chip inductor has been used in the current design. Another important and the most critical challenge is to implement a very high tuning range, high Q-factor on-chip varactor in standard CMOS process. In this research a new body driven varactor, which is forced to operate in accumulation mode has been developed and analyzed elaborately. The tuning range specification for the design was chosen to be 200 MHz accounting for component tolerance. Various means of measuring phase noise has been elaborately analyzed. Also detailed study on improving the noise performance of the LC-VCO has been studied.

Abstract: The design of voltage-controlled Oscillators nowadays is all about being capable of operating at higher clock frequencies for the purpose of higher data rate, consuming less power for the purpose of longer battery life, and having better phase noise performance for the purpose of higher quality of wireless service and more efficient use of the available frequency spectrum since most of the wireless and mobile terminals that these VCOs work in are required to be able to operate in multiple RF standards to serve new generations of standards while being backward compatible with existing ones, leading to a demand for multi-standard multi-band radio operation that deals with high frequency RF signals that undergo different modulation schemes of different standards in different channels over a wide range of frequency band. A top-down system design from the PLL to the VCO is carried out to determine the specifications for a fully integrated dual-band voltage-controlled oscillator (VCO) designed for a Zero-IF WiMAX/WLAN receiver in a O.18tm CMOS technology with 1.8V supply voltage. A VCO employing a differential cross-coupled inductance-capacitance (LC) tank architecture is proposed to cover twice the desired frequency bands for WiMAX and WLAN standards in order to avoid load pulling between VCO frequency and incoming RF frequency. The switching between two bands is implemented by using two binary-weighted capacitor arrays while switching inside each sub-band is implemented by different digital control signal combinations for the binary-weighted capacitances. A phase noise of -120.7dB/Hz at 1MHz offset frequency is demonstrated for an oscillation frequency of 4.84GHz. The average power consumption of this VCO is 8.1mW. This VCO is developed as an IP (Intellectual Property) to be used in a fully integrated CMOS multi-standard WiMAX/WLAN radio allowing seamless roaming of handheld mobile devices between hotspots in future Wireless Metropolitan Area Network (WMAN). To compare the performance of ring oscillators to that of LC tank oscillators, the designs of two three-stage multiple-pass voltage-controlled ring oscillators with dual-delay paths are demonstrated where the differential delay cell utilizes both the primary loop delay and the negative skewed delay to increase the frequency of oscillation substantially and retain or even increase tuning range. Their phase noise performance is also improved by switching in and out the transistors periodically. In design I, the covered frequency range is from 0.74 GHz to 1.96 GHz, which translates to a tuning range of 90 % A phase noise of -104.995dBc/Hz is demonstrated for an oscillation frequency of 1.8535 GHz. Each stage draws a current of 4.963mA on average from a 1.8V power supply, resulting in a power consumption of 26.8mW. In design II, the covered frequency range is from 1.0478 GHz to 2.0022 GHz, which translates to a tuning range of 63%. The frequency-voltage curve is almost a perfect linear curve for V between OV and 0.9V. A phase noise of -110.O45dBc/Hz is demonstrated for an oscillation frequency of 2.00216 GHz. Each stage draws a current of 10.179mA on average from a 1.8V power supply, resulting in a power consumption of 55mW.