Low-Noise Low-Power Design for Phase-Locked Loops
Title | Low-Noise Low-Power Design for Phase-Locked Loops PDF eBook |
Author | Feng Zhao |
Publisher | Springer |
Pages | 106 |
Release | 2014-11-25 |
Genre | Technology & Engineering |
ISBN | 3319122002 |
This book introduces low-noise and low-power design techniques for phase-locked loops and their building blocks. It summarizes the noise reduction techniques for fractional-N PLL design and introduces a novel capacitive-quadrature coupling technique for multi-phase signal generation. The capacitive-coupling technique has been validated through silicon implementation and can provide low phase-noise and accurate I-Q phase matching, with low power consumption from a super low supply voltage. Readers will be enabled to pick one of the most suitable QVCO circuit structures for their own designs, without additional effort to look for the optimal circuit structure and device parameters.
Analysis and Design of a Low-power Low-noise CMOS Phase-locked Loop
Title | Analysis and Design of a Low-power Low-noise CMOS Phase-locked Loop PDF eBook |
Author | Cheng Zhang |
Publisher | |
Pages | 0 |
Release | 2012 |
Genre | Electronic noise |
ISBN |
This thesis covers the analysis, design and simulation of a low-power low-noise CMOS Phase-Locked Loop (PLL). Starting with the PLL basics, this thesis discussed the PLL loop dynamics and behavioral modeling. In this thesis, the detailed design and implementation of individual building blocks of the low-power low-noise PLL have been presented. In order to improve the PLL performance, several novel architectural solutions has been proposed. To reduce the effect of blind-zone and extend the detection range of Phase Frequency Detector (PFD), we proposed the Delayed-Input-Edge PFD (DIE-PFD) and the Delayed-Input-Pulse PFD (DIP-PFD) with improved performance. We also proposed a NMOS-switch high-swing cascode charge pump that significantly reduces the output current mismatches. Voltage Controlled Oscillator (VCO) consumes the most power and dominates the noise in the PLL. A differential ring VCO with 550MHz to 950MHz tuning range has been designed, with the power consumption of the VCO is 2.5mW and the phase noise -105.2dBc/Hz at 1MHz frequency offset. Finally, the entire PLL system has been simulated to observe the overall performance. With input reference clock frequency equal 50MHz, the PLL is able to produce an 800MHz output frequency with locking time 400ns. The power consumption of the PLL system is 2.6mW and the phase noise at 1MHz frequency offset is -119dBc/Hz. The designs are implemented using IBM 0.13æm CMOS technology.
Design of Low Phase Noise Low Power CMOS Phase Locked Loops
Title | Design of Low Phase Noise Low Power CMOS Phase Locked Loops PDF eBook |
Author | |
Publisher | |
Pages | |
Release | |
Genre | |
ISBN |
Design of Low Phase Noise Low Power CMOS Phase Locked Loops
Title | Design of Low Phase Noise Low Power CMOS Phase Locked Loops PDF eBook |
Author | Xiantian Shi |
Publisher | |
Pages | 0 |
Release | 2008 |
Genre | |
ISBN |
The Design of Low Noise Oscillators
Title | The Design of Low Noise Oscillators PDF eBook |
Author | Ali Hajimiri |
Publisher | Springer Science & Business Media |
Pages | 214 |
Release | 2007-05-08 |
Genre | Technology & Engineering |
ISBN | 0306481995 |
It is hardly a revelation to note that wireless and mobile communications have grown tremendously during the last few years. This growth has placed stringent requi- ments on channel spacing and, by implication, on the phase noise of oscillators. C- pounding the challenge has been a recent drive toward implementations of transceivers in CMOS, whose inferior 1/f noise performance has usually been thought to disqualify it from use in all but the lowest-performance oscillators. Low noise oscillators are also highly desired in the digital world, of course. The c- tinued drive toward higher clock frequencies translates into a demand for ev- decreasing jitter. Clearly, there is a need for a deep understanding of the fundamental mechanisms g- erning the process by which device, substrate, and supply noise turn into jitter and phase noise. Existing models generally offer only qualitative insights, however, and it has not always been clear why they are not quantitatively correct.
Monolithic Phase-Locked Loops and Clock Recovery Circuits
Title | Monolithic Phase-Locked Loops and Clock Recovery Circuits PDF eBook |
Author | Behzad Razavi |
Publisher | John Wiley & Sons |
Pages | 516 |
Release | 1996-04-18 |
Genre | Technology & Engineering |
ISBN | 9780780311497 |
Featuring an extensive 40 page tutorial introduction, this carefully compiled anthology of 65 of the most important papers on phase-locked loops and clock recovery circuits brings you comprehensive coverage of the field-all in one self-contained volume. You'll gain an understanding of the analysis, design, simulation, and implementation of phase-locked loops and clock recovery circuits in CMOS and bipolar technologies along with valuable insights into the issues and trade-offs associated with phase locked systems for high speed, low power, and low noise.
Pll Performance, Simulation and Design
Title | Pll Performance, Simulation and Design PDF eBook |
Author | Dean Banerjee |
Publisher | Dog Ear Publishing |
Pages | 346 |
Release | 2006-08 |
Genre | Frequency modulation detectors |
ISBN | 1598581341 |
This book is intended for the reader who wishes to gain a solid understanding of Phase Locked Loop architectures and their applications. It provides a unique balance between both theoretical perspectives and practical design trade-offs. Engineers faced with real world design problems will find this book to be a valuable reference providing example implementations, the underlying equations that describe synthesizer behavior, and measured results that will improve confidence that the equations are a reliable predictor of system behavior. New material in the Fourth Edition includes partially integrated loop filter implementations, voltage controlled oscillators, and modulation using the PLL.