Nowadays over 50% of integrated circuits are fabricated at wafer foundries. This book presents a foundry-integrated perspective of the field and is a comprehensive and up-to-date manual designed to serve process, device, layout, and design engineers. It comprises chapters carefully selected to cover topics relevant for them to deal with their work. The book provides an insight into the different types of design rules (DRs) and considerations for setting new DRs. It discusses isolation, gate patterning, S/D contacts, metal lines, MOL, air gaps, and so on. It explains in detail the layout rules needed to support advanced planarization processes, different types of dummies, and related utilities as well as presents a large set of guidelines and layout-aware modeling for RF CMOS and analog modules. It also discusses the layout DRs for different mobility enhancement techniques and their related modeling, listing many of the dedicated rules for static random-access memory (SRAM), embedded polyfuse (ePF), and LogicNVM. The book also provides the setting and calibration of the process parameters set and describes the 28~20 nm planar MOSFET process flow for low-power and high-performance mobile applications in a step-by-step manner. It includes FEOL and BEOL physical and environmental tests for qualifications together with automotive qualification and design for automotive (DfA). Written for the professionals, the book belongs to the bookshelf of microelectronic discipline experts.

Learn to assess electromigration reliability and design more resilient chips in this comprehensive and practical resource. Beginning with fundamental physics and building to advanced methodologies, this book enables the reader to develop highly reliable on-chip wiring stacks and power grids. Through a detailed review on the role of microstructure, interfaces and processing on electromigration reliability, as well as characterisation, testing and analysis, the book follows the development of on-chip interconnects from microscale to nanoscale. Practical modeling methodologies for statistical analysis, from simple 1D approximation to complex 3D description, can be used for step-by-step development of reliable on-chip wiring stacks and industrial-grade power/ground grids. This is an ideal resource for materials scientists and reliability and chip design engineers.