This book constitutes the refereed proceedings of the 10th International Workshop on Power and Timing Modeling, Optimization and Simulation, PATMOS 2000, held in Göttingen, Germany in September 2000. The 33 revised full papers presented were carefully reviewed and selected for inclusion in the book. The papers are organized in sections on RTL power modeling, power estimation and optimization, system-level design, transistor level design, asynchronous circuit design, power efficient technologies, design of multimedia processing applications, adiabatic design and arithmetic modules, and analog-digital circuit modeling.

The International Workshop on Power and Timing Modeling, Optimization, and Simulation PATMOS 2002, was the 12th in a series of international workshops 1 previously held in several places in Europe. PATMOS has over the years evolved into a well-established and outstanding series of open European events on power and timing aspects of integrated circuit design. The increased interest, espe- ally in low-power design, has added further momentum to the interest in this workshop. Despite its growth, the workshop can still be considered as a very - cused conference, featuring high-level scienti?c presentations together with open discussions in a free and easy environment. This year, the workshop has been opened to both regular papers and poster presentations. The increasing number of worldwide high-quality submissions is a measure of the global interest of the international scienti?c community in the topics covered by PATMOS. The objective of this workshop is to provide a forum to discuss and inves- gate the emerging problems in the design methodologies and CAD-tools for the new generation of IC technologies. A major emphasis of the technical program is on speed and low-power aspects with particular regard to modeling, char- terization, design, and architectures. The technical program of PATMOS 2002 included nine sessions dedicated to most important and current topics on power and timing modeling, optimization, and simulation. The three invited talks try to give a global overview of the issues in low-power and/or high-performance circuit design.

This book constitutes the refereed proceedings of the 15th International Workshop on Power and Timing Optimization and Simulation, PATMOS 2005, held in Leuven, Belgium in September 2005. The 74 revised full papers presented were carefully reviewed and selected from numerous submissions. The papers are organized in topical sections on low-power processors, code optimization for low-power, high-level design, telecommunications and signal processing, low-power circuits, system-on-chip design, busses and interconnections, modeling, design automation, low-power techniques, memory and register files, applications, digital circuits, and analog and physical design.

This book constitutes the refereed proceedings of the 21st International Conference on Integrated Circuit and System Design, PATMOS 2011, held in Madrid, Spain, in September 2011. The 34 revised full papers presented were carefully reviewed and selected from numerous submissions. The paper feature emerging challenges in methodologies and tools for the design of upcoming generations of integrated circuits and systems and focus especially on timing, performance and power consumption as well as architectural aspects with particular emphasis on modeling, design, characterization, analysis and optimization.

This book constitutes the refereed proceedings of the 13th International Workshop on Power and Timing Modeling, Optimization and Simulation, PATMOS 2003, held in Torino, Italy in September 2003. The 43 revised full papers and 18 revised poster papers presented together with three keynote contributions were carefully reviewed and selected from 85 submissions. The papers are organized in topical sections on gate-level modeling and characterization, interconnect modeling and optimization, asynchronous techniques, RTL power modeling and memory optimization, high-level modeling, power-efficient technologies and designs, communication modeling and design, and low-power issues in processors and multimedia.

This book constitutes the thoroughly refereed post-conference proceedings of 19th International Workshop on Power and Timing Modeling, Optimization and Simulation, PATMOS 2009, featuring Integrated Circuit and System Design, held in Delft, The Netherlands during September 9-11, 2009. The 26 revised full papers and 10 revised poster papers presented were carefully reviewed and selected from numerous submissions. The papers are organized in topical sections on variability & statistical timing, circuit level techniques, power management, low power circuits & technology, system level techniques, power & timing optimization techniques, self-timed circuits, low power circuit analysis & optimization, and low power design studies.

Welcome to the proceedings of PATMOS 2008, the 18th in a series of int- national workshops. PATMOS 2008 was organized by INESC-ID / IST - TU Lisbon, Portugal, with sponsorship by Cadence, IBM, Chipidea, and Tecmic, and technical co-sponsorship by the IEEE. Over the years, PATMOS has evolved into an important European event, where researchers from both industry and academia discuss and investigate the emerging challenges in future and contemporary applications, design meth- ologies, and tools required for the development of the upcoming generations of integrated circuits and systems. The technical program of PATMOS 2008 c- tained state-of-the-art technical contributions, three invited talks, and a special session on recon?gurable architectures. The technical program focused on t- ing, performance and power consumption, as well as architectural aspects with particular emphasis on modeling, design, characterization, analysis and op- mization in the nanometer era. The Technical Program Committee, with the assistance of additional expert reviewers, selected the 41 papers presented at PATMOS. The papers were - ganized into 7 oral sessions (with a total of 31 papers) and 2 poster sessions (with a total of 10 papers). As is customary for the PATMOS workshops, full papers were required for review, and a minimum of three reviews were received per manuscript.