MOS Integral Circuit Design aims to help in the design of integrated circuits, especially large-scale ones, using MOS Technology through teaching of techniques, practical applications, and examples. The book covers topics such as design equation and process parameters; MOS static and dynamic circuits; logic design techniques, system partitioning, and layout techniques. Also featured are computer aids such as logic simulation and mask layout, as well as examples on simple MOS design. The text is recommended for electrical engineers who would like to know how to use MOS for integral circuit design.

Presenting a comprehensive overview of the design automation algorithms, tools, and methodologies used to design integrated circuits, the Electronic Design Automation for Integrated Circuits Handbook is available in two volumes. The second volume, EDA for IC Implementation, Circuit Design, and Process Technology, thoroughly examines real-time logic to GDSII (a file format used to transfer data of semiconductor physical layout), analog/mixed signal design, physical verification, and technology CAD (TCAD). Chapters contributed by leading experts authoritatively discuss design for manufacturability at the nanoscale, power supply network design and analysis, design modeling, and much more. Save on the complete set.

Three-Dimensional Integrated Circuit Design, Second Eition, expands the original with more than twice as much new content, adding the latest developments in circuit models, temperature considerations, power management, memory issues, and heterogeneous integration. 3-D IC experts Pavlidis, Savidis, and Friedman cover the full product development cycle throughout the book, emphasizing not only physical design, but also algorithms and system-level considerations to increase speed while conserving energy. A handy, comprehensive reference or a practical design guide, this book provides effective solutions to specific challenging problems concerning the design of three-dimensional integrated circuits. Expanded with new chapters and updates throughout based on the latest research in 3-D integration: Manufacturing techniques for 3-D ICs with TSVs Electrical modeling and closed-form expressions of through silicon vias Substrate noise coupling in heterogeneous 3-D ICs Design of 3-D ICs with inductive links Synchronization in 3-D ICs Variation effects on 3-D ICs Correlation of WID variations for intra-tier buffers and wires Offers practical guidance on designing 3-D heterogeneous systems Provides power delivery of 3-D ICs Demonstrates the use of 3-D ICs within heterogeneous systems that include a variety of materials, devices, processors, GPU-CPU integration, and more Provides experimental case studies in power delivery, synchronization, and thermal characterization

We live in a time of great change. In the electronics world, the last several decades have seen unprecedented growth and advancement, described by Moore’s law. This observation stated that transistor density in integrated circuits doubles every 1. 5–2 years. This came with the simultaneous improvement of individual device perf- mance as well as the reduction of device power such that the total power of the resulting ICs remained under control. No trend remains constant forever, and this is unfortunately the case with Moore’s law. The trouble began a number of years ago when CMOS devices were no longer able to proceed along the classical scaling trends. Key device parameters such as gate oxide thickness were simply no longer able to scale. As a result, device o- state currents began to creep up at an alarming rate. These continuing problems with classical scaling have led to a leveling off of IC clock speeds to the range of several GHz. Of course, chips can be clocked higher but the thermal issues become unmanageable. This has led to the recent trend toward microprocessors with mul- ple cores, each running at a few GHz at the most. The goal is to continue improving performance via parallelism by adding more and more cores instead of increasing speed. The challenge here is to ensure that general purpose codes can be ef?ciently parallelized. There is another potential solution to the problem of how to improve CMOS technology performance: three-dimensional integrated circuits (3D ICs).

A practical guide to the effects of radiation on semiconductor components of electronic systems, and techniques for the designing, laying out, and testing of hardened integrated circuits This book teaches the fundamentals of radiation environments and their effects on electronic components, as well as how to design, lay out, and test cost-effective hardened semiconductor chips not only for today’s space systems but for commercial terrestrial applications as well. It provides a historical perspective, the fundamental science of radiation, and the basics of semiconductors, as well as radiation-induced failure mechanisms in semiconductor chips. Integrated Circuits Design for Radiation Environments starts by introducing readers to semiconductors and radiation environments (including space, atmospheric, and terrestrial environments) followed by circuit design and layout. The book introduces radiation effects phenomena including single-event effects, total ionizing dose damage and displacement damage) and shows how technological solutions can address both phenomena. Describes the fundamentals of radiation environments and their effects on electronic components Teaches readers how to design, lay out and test cost-effective hardened semiconductor chips for space systems and commercial terrestrial applications Covers natural and man-made radiation environments, space systems and commercial terrestrial applications Provides up-to-date coverage of state-of-the-art of radiation hardening technology in one concise volume Includes questions and answers for the reader to test their knowledge Integrated Circuits Design for Radiation Environments will appeal to researchers and product developers in the semiconductor, space, and defense industries, as well as electronic engineers in the medical field. The book is also helpful for system, layout, process, device, reliability, applications, ESD, latchup and circuit design semiconductor engineers, along with anyone involved in micro-electronics used in harsh environments.

All aspects of chip realization for both digital and analog circuits are covered. Electronics engineers are shown how to choose appropriate technololgy and circuit architecture, and plan the IC design. They'll gain expert information on power consaiderations, the advantages and disadvantages of each IC architecture, and aspects of design for testability.