Abstract: "We present the methods used in the implementation of an incremental zero/unit-delay switch-level logic simulator for MOS circuits based on the MOSSIM II switch-level model. The incremental simulator is embedded within a single fully-integrated capture/compile/simulate tool. Modifications to the design at any level in the structural design hierarchy are automatically mapped into changes in the underlying transistor netlist and the incremental simulator is triggered to quickly resimulate only those regions of the circuit whose behavior has been modified by the change."

This description of the structure of simulators suitable for use in the design of digital electronic systems includes the compiled code and event driven algorithms for digital electronic system simulators, together with timing verification as well as structural limitations and problems.

The proceedings of the conference held in Anaheim, California, June 1992, comprise 125 papers organized into 44 sessions. There is increased emphasis on presentations (short tutorials, panels, and selected papers) of interest to the design automation user community, with a better balance between the