This book provides a structured treatment of the key principles and techniques for enabling efficient processing of deep neural networks (DNNs). DNNs are currently widely used for many artificial intelligence (AI) applications, including computer vision, speech recognition, and robotics. While DNNs deliver state-of-the-art accuracy on many AI tasks, it comes at the cost of high computational complexity. Therefore, techniques that enable efficient processing of deep neural networks to improve key metrics—such as energy-efficiency, throughput, and latency—without sacrificing accuracy or increasing hardware costs are critical to enabling the wide deployment of DNNs in AI systems. The book includes background on DNN processing; a description and taxonomy of hardware architectural approaches for designing DNN accelerators; key metrics for evaluating and comparing different designs; features of DNN processing that are amenable to hardware/algorithm co-design to improve energy efficiency and throughput; and opportunities for applying new technologies. Readers will find a structured introduction to the field as well as formalization and organization of key concepts from contemporary work that provide insights that may spark new ideas.

This book provides a structured introduction of the key concepts and techniques that enable in-/near-memory computing. For decades, processing-in-memory or near-memory computing has been attracting growing interest due to its potential to break the memory wall. Near-memory computing moves compute logic near the memory, and thereby reduces data movement. Recent work has also shown that certain memories can morph themselves into compute units by exploiting the physical properties of the memory cells, enabling in-situ computing in the memory array. While in- and near-memory computing can circumvent overheads related to data movement, it comes at the cost of restricted flexibility of data representation and computation, design challenges of compute capable memories, and difficulty in system and software integration. Therefore, wide deployment of in-/near-memory computing cannot be accomplished without techniques that enable efficient mapping of data-intensive applications to such devices, without sacrificing accuracy or increasing hardware costs excessively. This book describes various memory substrates amenable to in- and near-memory computing, architectural approaches for designing efficient and reliable computing devices, and opportunities for in-/near-memory acceleration of different classes of applications.

This book offers a balanced and comprehensive guide to the core principles, fundamental properties, experimental approaches, and state-of-the-art applications of two major groups of emerging non-volatile memory technologies, i.e. spintronics-based devices as well as resistive switching devices, also known as Resistive Random Access Memory (RRAM). The first section presents different types of spintronic-based devices, i.e. magnetic tunnel junction (MTJ), domain wall, and skyrmion memory devices. This section describes how their developments have led to various promising applications, such as microwave oscillators, detectors, magnetic logic, and neuromorphic engineered systems. In the second half of the book, the underlying device physics supported by different experimental observations and modelling of RRAM devices are presented with memory array level implementation. An insight into RRAM desired properties as synaptic element in neuromorphic computing platforms from material and algorithms viewpoint is also discussed with specific example in automatic sound classification framework.

In this book, a global team of experts from academia, research institutes and industry presents their vision on how new nano-chip architectures will enable the performance and energy efficiency needed for AI-driven advancements in autonomous mobility, healthcare, and man-machine cooperation. Recent reviews of the status quo, as presented in CHIPS 2020 (Springer), have prompted the need for an urgent reassessment of opportunities in nanoelectronic information technology. As such, this book explores the foundations of a new era in nanoelectronics that will drive progress in intelligent chip systems for energy-efficient information technology, on-chip deep learning for data analytics, and quantum computing. Given its scope, this book provides a timely compendium that hopes to inspire and shape the future of nanoelectronics in the decades to come.

Artificial Intelligence (AI) has found many applications in the past decade due to the ever increasing computing power. Artificial Neural Networks are inspired in the brain structure and consist in the interconnection of artificial neurons through artificial synapses. Training these systems requires huge amounts of data and, after the network is trained, it can recognize unforeseen data and provide useful information. The so-called Spiking Neural Networks behave similarly to how the brain functions and are very energy efficient. Up to this moment, both spiking and conventional neural networks have been implemented in software programs running on conventional computing units. However, this approach requires high computing power, a large physical space and is energy inefficient. Thus, there is an increasing interest in developing AI tools directly implemented in hardware. The first hardware demonstrations have been based on CMOS circuits for neurons and specific communication protocols for synapses. However, to further increase training speed and energy efficiency while decreasing system size, the combination of CMOS neurons with memristor synapses is being explored. The memristor is a resistor with memory which behaves similarly to biological synapses. This book explores the state-of-the-art of neuromorphic circuits implementing neural networks with memristors for AI applications.

This book describes the state-of-the-art of technology and research on In-Memory Computing Hardware Accelerators for Data-Intensive Applications. The authors discuss how processing-centric computing has become insufficient to meet target requirements and how Memory-centric computing may be better suited for the needs of current applications. This reveals for readers how current and emerging memory technologies are causing a shift in the computing paradigm. The authors do deep-dive discussions on volatile and non-volatile memory technologies, covering their basic memory cell structures, operations, different computational memory designs and the challenges associated with them. Specific case studies and potential applications are provided along with their current status and commercial availability in the market.

Quality Electronic Design (QED)’s landscape spans a vast region where territories of many participating disciplines and technologies overlap. This book explores the latest trends in several key topics related to quality electronic design, with emphasis on Hardware Security, Cybersecurity, Machine Learning, and application of Artificial Intelligence (AI). The book includes topics in nonvolatile memories (NVM), Internet of Things (IoT), FPGA, and Neural Networks.