Various approaches for finding optimal values for the parameters of analog cells have made their entrance in commercial applications. However, a larger impact on the performance is expected if tools are developed which operate on a higher abstraction level and consider multiple architectural choices to realize a particular functionality. This book examines the opportunities, conditions, problems, solutions and systematic methodologies for this new generation of analog CAD tools.

The tools and techniques you need to break the analog design bottleneck! Ten years ago, analog seemed to be a dead-end technology. Today, System-on-Chip (SoC) designs are increasingly mixed-signal designs. With the advent of application-specific integrated circuits (ASIC) technologies that can integrate both analog and digital functions on a single chip, analog has become more crucial than ever to the design process. Today, designers are moving beyond hand-crafted, one-transistor-at-a-time methods. They are using new circuit and physical synthesis tools to design practical analog circuits; new modeling and analysis tools to allow rapid exploration of system level alternatives; and new simulation tools to provide accurate answers for analog circuit behaviors and interactions that were considered impossible to handle only a few years ago. To give circuit designers and CAD professionals a better understanding of the history and the current state of the art in the field, this volume collects in one place the essential set of analog CAD papers that form the foundation of today's new analog design automation tools. Areas covered are: * Analog synthesis * Symbolic analysis * Analog layout * Analog modeling and analysis * Specialized analog simulation * Circuit centering and yield optimization * Circuit testing Computer-Aided Design of Analog Integrated Circuits and Systems is the cutting-edge reference that will be an invaluable resource for every semiconductor circuit designer and CAD professional who hopes to break the analog design bottleneck.

This book describes new tools for front end analog designers, starting with global variation-aware sizing, and extending to novel variation-aware topology design. The tools aid design through automation, but more importantly, they also aid designer insight through automation. We now describe four design tasks, each more general than the previous, and how this book contributes design aids and insight aids to each. The ?rst designer task targeted is global robust sizing. This task is supported by a design tool that does automated, globally reliable, variation-aware s- ing (SANGRIA),and an insight-aiding tool that extracts designer-interpretable whitebox models that relate sizings to circuit performance (CAFFEINE). SANGRIA searches on several levels of problem dif?culty simultaneously, from lower cheap-to-evaluate “exploration” layers to higher full-evaluation “exploitation” layers (structural homotopy). SANGRIAmakes maximal use of circuit simulations by performing scalable data mining on simulation results to choose new candidate designs. CAFFEINE accomplishes its task by tre- ing function induction as a tree-search problem. It constrains its tree search space via a canonical-functional-form grammar, and searches the space with grammatically constrained genetic programming. The second designer task is topology selection/topology design. Topology selection tools must consider a broad variety of topologies such that an app- priate topology is selected, must easily adapt to new semiconductor process nodes, and readily incorporate new topologies. Topology design tools must allow designers to creatively explore new topology ideas as rapidly as possible.

Reliability concerns and the limitations of process technology can sometimes restrict the innovation process involved in designing nano-scale analog circuits. The success of nano-scale analog circuit design requires repeat experimentation, correct analysis of the device physics, process technology, and adequate use of the knowledge database. Starting with the basics, Nano-Scale CMOS Analog Circuits: Models and CAD Techniques for High-Level Design introduces the essential fundamental concepts for designing analog circuits with optimal performances. This book explains the links between the physics and technology of scaled MOS transistors and the design and simulation of nano-scale analog circuits. It also explores the development of structured computer-aided design (CAD) techniques for architecture-level and circuit-level design of analog circuits. The book outlines the general trends of technology scaling with respect to device geometry, process parameters, and supply voltage. It describes models and optimization techniques, as well as the compact modeling of scaled MOS transistors for VLSI circuit simulation. • Includes two learning-based methods: the artificial neural network (ANN) and the least-squares support vector machine (LS-SVM) method • Provides case studies demonstrating the practical use of these two methods • Explores circuit sizing and specification translation tasks • Introduces the particle swarm optimization technique and provides examples of sizing analog circuits • Discusses the advanced effects of scaled MOS transistors like narrow width effects, and vertical and lateral channel engineering Nano-Scale CMOS Analog Circuits: Models and CAD Techniques for High-Level Design describes the models and CAD techniques, explores the physics of MOS transistors, and considers the design challenges involving statistical variations of process technology parameters and reliability constraints related to circuit design.

Technology plays a vital role in bridging the digital divide and fostering sustainability in educational development. This is evident through the successful use of social media in educational marketing campaigns and through the integration of massive open online courses to reorient learner interactions in higher education environments. Marketing Initiatives for Sustainable Educational Development contains the latest approaches to maximize self-guided, interdisciplinary learning through the use of strategies such as web-based games to elicit collaborative behavior in student groups. It also explores the important role that technology serves in educating students, especially in the realm of technological skills and competencies. This book is a vital resource for educators, instructional designers, administrators, marketers, and education professionals seeking to enhance student learning and engagement through technology-based learning tools.

Realizing maximum performance from high bit-rate and RF circuits requires close attention to IC technology, circuit-to-circuit interconnections (i.e., the ‘interconnect’) and circuit design. This detailed book covers each of these topics from theory to practice, with sufficient detail to help you produce circuits that are ‘first-time right’. Many practical circuit examples are included to demonstrate the interplay between technology, interconnect and circuit design.

Low-Power High-Speed ADCs for Nanometer CMOS Integration is about the design and implementation of ADC in nanometer CMOS processes that achieve lower power consumption for a given speed and resolution than previous designs, through architectural and circuit innovations that take advantage of unique features of nanometer CMOS processes. A phase lock loop (PLL) clock multiplier has also been designed using new circuit techniques and successfully tested. 1) A 1.2V, 52mW, 210MS/s 10-bit two-step ADC in 130nm CMOS occupying 0.38mm2. Using offset canceling comparators and capacitor networks implemented with small value interconnect capacitors to replace resistor ladder/multiplexer in conventional sub-ranging ADCs, it achieves 74dB SFDR for 10MHz and 71dB SFDR for 100MHz input. 2) A 32mW, 1.25GS/s 6-bit ADC with 2.5GHz internal clock in 130nm CMOS. A new type of architecture that combines flash and SAR enables the lowest power consumption, 6-bit >1GS/s ADC reported to date. This design can be a drop-in replacement for existing flash ADCs since it does require any post-processing or calibration step and has the same latency as flash. 3) A 0.4ps-rms-jitter (integrated from 3kHz to 300MHz offset for >2.5GHz) 1-3GHz tunable, phase-noise programmable clock-multiplier PLL for generating sampling clock to the SAR ADC. A new loop filter structure enables phase error preamplification to lower PLL in-band noise without increasing loop filter capacitor size.