This book introduces power amplifier design in 22nm FDSOI CMOS dedicated towards 5G applications at 28 GHz and presents 4 state-of-the-art power amplifier designs. The authors discuss power amplifier performance metrics, design trade-offs, and presents different power amplifier classes utilizing efficiency enhancement techniques at 28 GHz. The book presents the design process from theory, simulation, layout, and finally measurement results.

This book focuses on broadband power amplifier design for wireless communication. Nonlinear model embedding is described as a powerful tool for designing broadband continuous Class-J and continuous class F power amplifiers. The authors also discuss various techniques for extending bandwidth of load modulation based power amplifiers, such as Doherty power amplifier and Chireix outphasing amplifiers. The book also covers recent trends on digital as well as analog techniques to enhance bandwidth and linearity in wireless transmitters. Presents latest trends in designing broadband power amplifiers; Covers latest techniques for using nonlinear model embedding in designing power amplifiers based on waveform engineering; Describes the latest techniques for extending bandwidth of load modulation based power amplifiers such as Doherty power amplifier and Chireix outphasing amplifiers; Includes coverage of hybrid analog/digital predistortion as wideband solution for wireless transmitters; Discusses recent trends on on-chip power amplifier design with GaN /GaAs MMICs for high frequency applications.

This book focuses on the development of design techniques and methodologies for 60-GHz and E-band power amplifiers and transmitters at device, circuit and layout levels. The authors show the recent development of millimeter-wave design techniques, especially of power amplifiers and transmitters, and presents novel design concepts, such as “power transistor layout” and “4-way parallel-series power combiner”, that can enhance the output power and efficiency of power amplifiers in a compact silicon area. Five state-of-the-art 60-GHz and E-band designs with measured results are demonstrated to prove the effectiveness of the design concepts and hands-on methodologies presented. This book serves as a valuable reference for circuit designers to develop millimeter-wave building blocks for future 5G applications.

The emerging 5G and mm-wave high data rate wireless communication applications have exacerbated the challenges of the PA design, especially for the commercial Si-based ICs. The complex wideband OFDM signals in these applications, with high PAPR, demand stringent PA requirements of linearity, and efficiency at both peak and backoff power levels. This dissertation addresses the design challenges for sub-6GHz and 28GHz CMOS and SiGe integrated PAs, by introducing novel techniques and presenting them with proper mathematical framework and modeling, alongside the hardware implementations that achieve record results. Active load modulation, employed in Doherty and Chireix outphasing architectures, is one of the well-known techniques to improve the backoff efficiency of PAs. In theory, outphasing offers a better efficiency profile than Doherty, but it was traditionally believed that it works well only with voltage-mode PAs. However, recently it has been shown that for outphasing with current-mode PAs, if the input drive power reduced at backoff, good results can be achieved. In this dissertation a detailed mathematical analysis for current-mode outphasing is presented, and then the implemented 5.5GHz 45nm CMOS-SOI dual-input outphasing PA is discussed that achieves record average PAE of 30.9% while generating a 40MHz 64-QAM OFDM modulated signal with 7.9dB PAPR and 14dBm average output power. At 28GHz band, the loss due to the integrated passive elements is one of the bottlenecks to achieve high efficiency. To address this issue a novel Chiriex combiner based on a "triaxial balun" is presented. An equivalent circuit model of the balun is introduced for the first time to make the analysis and design more straight forward. The implemented chip in 130nm SiGe BiCMOS process shows balun loss of only 0.5dB at 28GHz, and the dual-input outphasing PA achieves a record average PAE of 25.3% for an 8.1dB PAPR, 80MHz 64-QAM OFDM signal with average output power of 14.3dBm. In phased array systems, it is not practical to employ individual digital predistortion (DPD) for each PA unit, and they must be inherently linear. A novel architecture named Single Input Linear Chireix (SILC) PA is introduced that not only has a high backoff efficiency but also has a linear response achieved by correcting the transistor related distortions using the systematic AM-AM and AM-PM variations. The implemented PA in 130nm SiGe process demonstrates 19dBm saturated output power with 34.4% peak PAE and 6-dB backoff PAE of >23% at 27.5GHz. The modulated signal performance using a 100MHz 64-QAM OFDM signal shows average output power of 11.9dBm with PAE >20%, EVM

Annotation This design guide collects 21 articles published in between 1989 and 2001, enabling readers to review classic theory as well as stay abreast of new technology. Coverage includes the specification, analysis, and measurement of distortion from various perspectives; predistortion techniques; and practical designs, including the magnetron, biasing LDMOS FETs for linear operation, the RF power transistor, and a push-pull 300-watt amplifier for 81.36 MHZ. Each article includes references. There is no index. Annotation c. Book News, Inc., Portland, OR (booknews.com).

With the race to next-generation millimeter-wave (mm-wave) fifth-generation (5G) wireless technology, implementation of highly power-efficient transceivers has become an important research topic. Particularly, the design of high-efficiency and frequency-reconfigurable power amplifier (PA) in complementary-metal-oxide-semiconductor (CMOS) technology is of paramount importance as it enables longer battery life and improved thermal management at a low cost in smart portable-devices while supporting multi-standard 5G communications such as 28GHz, 37-40GHz etc. Simultaneously, a PA with large-bandwidth and high-linearity is highly desirable for 5G mobile communications as it can cover multiple wideband-channels with high-order complex-modulation schemes (i.e., 64/512-quadrature-amplitude-modulation (QAM)) while ensuring robust performances against process-voltage-temperature variations. So far, traditional PA architectures have failed to address these critical design challenges and performance goals. This dissertation presents three new architectures for the design of highly-efficient, highly-linear, wideband and frequency-reconfigurable CMOS PAs for mm-wave 5G cellular communications with 15-16dBm of output-power. First, a 40% power-added-efficiency (PAE) frequency-reconfigurable PA with a tunable gate-drain neutralization at 24GHz and 28GHz is investigated in 65nm CMOS. This is the very first demonstration of a frequency-reconfigurable CMOS PA at mm-wave frequencies using tunable-inductor and tunable-transformer. Second, a 25-35GHz neutralized Continuous Class-F (CCF) CMOS PA achieving 26% modulation-PAE at 1.5Gbps and 46.4% peak-PAE is developed. This design is the very first demonstration of a CCF PA at mm-wave, and the reported measured 46.4% PAE is the highest PAE among mm-wave CMOS PAs to-date. Finally, a 28GHz 41%-PAE linear CMOS PA architecture using a transformer-based amplitude-to-phase (AM-PM) pre-distortion correction technique for 5G is investigated and developed. The proposed linearizer adopts a transformer-based self-compensated pre-distortion network to correct a detrimental AM-PM distortion due to non-linear gate-source capacitance (Cgs) in CMOS PAs. This linearization method mitigates the large-gain reduction problem in traditionally used capacitor-based linearization approaches while consuming no extra-power or introducing additional circuity. Subsequently, significant improvement in modulated-PAE and linearity is achieved. These three PA architectures provide distinct merits of advancing the knowledge of high-linearity, high-efficiency, wideband and frequency-reconfigurable fully-integrated CMOS PA design at mm-wave for next-generation multi-Gbps 5G communications by presenting original circuit topologies, fully supported by analytical-equations, chip-fabrication and comprehensive large-signal measurement results.

This book is focused on addressing the designs of FinFET-based analog ICs for 5G and E-band communication networks. In addition, it also incorporates some of the contemporary developments over different fields. It highlights the latest advances, problems and challenges and presents the latest research results in the field of mm-wave integrated circuits designing based on scientific literature and its practical realization. The traditional approaches are excluded in this book. The authors cover various design guidelines to be taken care for while designing these circuits and detrimental scaling effects on the same. Moreover, Gallium Nitrides (GaN) are also reported to show huge potentials for the power amplifier designing required in 5G communication network. Subsequently, to enhance the readability of this book, the authors also include real-time problems in RFIC designing, case studies from experimental results, and clearly demarking design guidelines for the 5G communication ICs designing. This book incorporates the most recent FinFET architecture for the analog IC designing and the scaling effects along with the GaN technology as well.