This book constitutes the thoroughly refereed post-proceedings of the Second International Workshop on Power-Aware Computer Systems, PACS 2002, held in Cambridge, MA, USA, in February 2002. The 13 revised full papers presented were carefully selected for inclusion in the book during two rounds of reviewing and revision. The papers are organized in topical sections on power-aware architecture and microarchitecture, power-aware real-time systems, power modeling and monitoring, and power-aware operating systems and compilers.

This synthesis lecture presents the current state-of-the-art in applying low-latency, lossless hardware compression algorithms to cache, memory, and the memory/cache link. There are many non-trivial challenges that must be addressed to make data compression work well in this context. First, since compressed data must be decompressed before it can be accessed, decompression latency ends up on the critical memory access path. This imposes a significant constraint on the choice of compression algorithms. Second, while conventional memory systems store fixed-size entities like data types, cache blocks, and memory pages, these entities will suddenly vary in size in a memory system that employs compression. Dealing with variable size entities in a memory system using compression has a significant impact on the way caches are organized and how to manage the resources in main memory. We systematically discuss solutions in the open literature to these problems. Chapter 2 provides the foundations of data compression by first introducing the fundamental concept of value locality. We then introduce a taxonomy of compression algorithms and show how previously proposed algorithms fit within that logical framework. Chapter 3 discusses the different ways that cache memory systems can employ compression, focusing on the trade-offs between latency, capacity, and complexity of alternative ways to compact compressed cache blocks. Chapter 4 discusses issues in applying data compression to main memory and Chapter 5 covers techniques for compressing data on the cache-to-memory links. This book should help a skilled memory system designer understand the fundamental challenges in applying compression to the memory hierarchy and introduce him/her to the state-of-the-art techniques in addressing them.

The book Operating System by Rohit Khurana is an insightful work that elaborates on fundamentals as well as advanced topics of the discipline. It offers an in-depth coverage of concepts, design and functions of an operating system irrespective of the hardware used. With illustrations and examples the aim is to make the subject crystal clear and the book extremely student-friendly. The book caters to undergraduate students of most Indian universities, who would find subject matter highly informative and enriching. Tailored as a guide for self-paced learning, it equips budding system programmers with the right knowledge and expertise. The book has been revised to keep pace with the latest technology and constantly revising syllabuses. Thus, this edition has become more comprehensive with the inclusion of several new topics. In addition, certain sections of the book have been thoroughly revised. Key Features • Case studies of Unix, Linux and Windows to put theory concepts into practice • A crisp summary for recapitulation with each chapter • A glossary of technical terms • Insightful questions and model test papers to prepare for the examinations New in this Edition • More types of operating system, like PC and mobile; Methods used for communication in client-server systems. • New topics like: Thread library; Thread scheduling; Principles of concurrency, Precedence graph, Concurrency conditions and Sleeping barber problem; Structure of page tables, Demand segmentation and Cache memory organization; STREAMS; Disk attachment, Stable and tertiary storage, Record blocking and File sharing; Goals and principles of protection, Access control matrix, Revocation of access rights, Cryptography, Trusted systems, and Firewalls.

Embedded Systems Architecture is a practical and technical guide to understanding the components that make up an embedded system's architecture. This book is perfect for those starting out as technical professionals such as engineers, programmers and designers of embedded systems; and also for students of computer science, computer engineering and electrical engineering. It gives a much-needed 'big picture' for recently graduated engineers grappling with understanding the design of real-world systems for the first time, and provides professionals with a systems-level picture of the key elements that can go into an embedded design, providing a firm foundation on which to build their skills. - Real-world approach to the fundamentals, as well as the design and architecture process, makes this book a popular reference for the daunted or the inexperienced: if in doubt, the answer is in here! - Fully updated with new coverage of FPGAs, testing, middleware and the latest programming techniques in C, plus complete source code and sample code, reference designs and tools online make this the complete package - Visit the companion web site at http://booksite.elsevier.com/9780123821966/ for source code, design examples, data sheets and more - A true introductory book, provides a comprehensive get up and running reference for those new to the field, and updating skills: assumes no prior knowledge beyond undergrad level electrical engineering - Addresses the needs of practicing engineers, enabling it to get to the point more directly, and cover more ground. Covers hardware, software and middleware in a single volume - Includes a library of design examples and design tools, plus a complete set of source code and embedded systems design tutorial materials from companion website