This thesis describes a tool that helps in analyzing the current execution state in the processing elements on a reconfigurable co-processor and facilitates an integrated HW/SW debug environment. The described tool has most of the functionality of a traditional hardware simulator and it executes faster than the simulator. This tool exploits the readback capabilities of Xilinx FPGA, through which the state of execution is extracted and is sent back to the general-purpose processor. This allows the user to identify problems in hardware logic for static and dynamic reconfiguration, since this tool is invoked from a software application running in debugged mode, the user has the ability to observe and control the hardware and software design simultaneously. This tool also helps in accelerating the hardware debugging by letting the design run on hardware till the user determined point of interest and then forcing the state of design into the hardware simulator for functional or timing simulation. Software debugging, which is well established, involves setting break points to halt the software upon execution of specific routines and line numbers, observing data structures, viewing the call stack and setting up watch-conditions. Hardware debugging includes monitoring the state of execution in the FPGA and determining co-processor board RAM and FIFO contents. In this thesis, an integrated hardware execution and simulation environment is presented to the user, providing many of the features found in a standard hardware simulator such as watch-points, clock stepping and signal probing. Hardware watch-points allows the hardware design to stop execution whenever a user-defined trigger condition is reached. This tool allows the user to step a user-defined number of clock cycles enabling easy recreation of the problem in hardware. Different approaches for adding watch-point logic into the design are presented, with the goal of minimizing the area overhead without affecting timing (maximum frequency) or the place and route time for the overall circuit. Providing flexibility to the user to support changing of watch-point conditions is an additional requirement. Automating watch-point logic identification in a placed and routed design and thus automating the change in its value is also described.

Rapid energy estimation for energy efficient applications using field-programmable gate arrays (FPGAs) remains a challenging research topic. Energy dissipation and efficiency have prevented the widespread use of FPGA devices in embedded systems, where energy efficiency is a key performance metric. Helping overcome these challenges, Energy Efficient Hardware-Software Co-Synthesis Using Reconfigurable Hardware offers solutions for the development of energy efficient applications using FPGAs. The book integrates various high-level abstractions for describing hardware and software platforms into a single, consistent application development framework, enabling users to construct, simulate, and debug systems. Based on these high-level concepts, it proposes an energy performance modeling technique to capture the energy dissipation behavior of both the reconfigurable hardware platform and the target applications running on it. The authors also present a dynamic programming-based algorithm to optimize the energy performance of an application running on a reconfigurable hardware platform. They then discuss an instruction-level energy estimation technique and a domain-specific modeling technique to provide rapid and fairly accurate energy estimation for hardware-software co-designs using reconfigurable hardware. The text concludes with example designs and illustrative examples that show how the proposed co-synthesis techniques lead to a significant amount of energy reduction. This book explores the advantages of using reconfigurable hardware for application development and looks ahead to future research directions in the field. It outlines the range of aspects and steps that lead to an energy efficient hardware-software application synthesis using FPGAs.

As the complexity of modern embedded systems increases, it becomes less practical to design monolithic processing platforms. As a result, reconfigurable computing is being adopted widely for more flexible design. Reconfigurable Computers offer the spatial parallelism and fine-grained customizability of application-specific circuits with the postfabrication programmability of software. To make the most of this unique combination of performance and flexibility, designers need to be aware of both hardware and software issues. FPGA users must think not only about the gates needed to perform a computation but also about the software flow that supports the design process. The goal of this book is to help designers become comfortable with these issues, and thus be able to exploit the vast opportunities possible with reconfigurable logic.

Configurable computing machines (CCMs) offer high-performance application acceleration with custom hardware. They are also dynamically reconfigurable and give significant internal visibility. Such features are useful throughout the design, debug, and deploy stages of CCM-based application development. However traditional, monolithic design tools do not offer adequate support for all of these development stages. This thesis describes a specification for a reconfigurable computing application framework (RCAF) which is more suitable for CCM application development. It also describes an implementation of such an RCAF. This RCAF improves the efficiency of application design and debugging. It also establishes an application architecture framework which helps to build up not only the hardware design, but also the application software and user interface. Applications built using this small, deployable RCAF may also perform significantly better due to the dynamic hardware reconfiguration features included with the RCAF.

This book constitutes the refereed proceedings of the 12th International Conference on Field-Programmable Logic and Applications, FPL 2002, held in Montpellier, France, in September 2002. The 104 revised regular papers and 27 poster papers presented together with three invited contributions were carefully reviewed and selected from 214 submissions. The papers are organized in topical sections on rapid prototyping, FPGA synthesis, custom computing engines, DSP applications, reconfigurable fabrics, dynamic reconfiguration, routing and placement, power estimation, synthesis issues, communication applications, new technologies, reconfigurable architectures, multimedia applications, FPGA-based arithmetic, reconfigurable processors, testing and fault-tolerance, crypto applications, multitasking, compilation techniques, etc.

This book constitutes the refereed proceedings of the 11th International Conference on Field-Programmable Logic and Application, FPL 2001, held in Belfast, Northern Ireland, UK, in August 2001. The 56 revised full papers and 15 short papers presented were carefully reviewed and selected from a total of 117 submissions. The book offers topical sections on architectural framework, place and route, architecture, DSP, synthesis, encryption, runtime reconfiguration, graphics and vision, networking, processor interaction, applications, methodology, loops and systolic, image processing, faults, and arithmetic.