Abstract: "In this paper, we study a hardware-supported, compiler-directed (HSCD) cache coherence scheme, which can be implemented on a large-scale multiprocessor using off-the-shelf microprocessors, such as the Cray T3D. The scheme can be adapted to various cache organizations, including multi-word cache lines and byte-addressable architectures. Several system related issues, including critical sections, inter-thread communication, and task migration have also been addressed. The cost of the required hardware support is minimal and proportional to the cache size. The necessary compiler algorithms, including intra- and interprocedural array data flow analysis, have been implemented on the Polaris parallelizing compiler [33]. From our simulation study using the Perfect Club benchmarks [5], we found that in spite of the conservative analysis made by the compiler, the performance of the proposed HSCD scheme can be comparable to that of a full-map hardware directory scheme. Given its comparable performance and reduced hardware cost, the proposed scheme can be a viable alternative for large-scale multiprocessors such as the Cray T3D, which rely on users to maintain data coherence."

Abstract: "Efficiently maintaining cache coherence is a major problem in large-scale shared memory multiprocessors. Hardware directory schemes have very high memory requirements, while software-directed schemes must rely on imprecise compile-time memory disambiguation. Recently proposed dynamic directory schemes allocate pointers to blocks only as they are referenced, which significantly reduces their memory requirements, but they still allocate pointers to blocks that do not need them. We show how compiler marking can further reduce the directory size by allocating pointers only when necessary. Using trace-driven simulations, we find that the performance of this new approach is comparable to other coherence schemes, but with significantly lower memory requirements."

The cache coherence maintenance problem has been the major obstacle in using private cache memory to reduce memory access latency in large-scale multiprocessor systems. Two compiler-directed solutions, the fast selective invalidation scheme and the version control scheme, are proposed in this work. Contrary to the existing hardware-based approach, the proposed schemes expose caches to software-directed management techniques which have the advantage of requiring no global communication and maintaining expandability of the multiprocessor systems. The fast selective scheme employs compile-time flow analysis techniques to detect cache data that contain obsolete values, and uses simple hardware to prevent using such data. The version control scheme defines the concept of version of a program variable to maintain up-to-date copies in the cache and solves the difficult problem of preserving temporal locality in parallel execution. Unlike existing software-directed schemes, both schemes achieve selective invalidation with very low time penalty. The version control scheme is also extended to hierarchical cache systems for which no satisfactory solutions exist. Detailed discussion on the development of these schemes and their proofs are presented. Finally, experimental data by simulation are shown to support the advantage of the schemes.