RETHINKING GLOBAL ROUTING FOR MODERN VLSI DESIGN: CONGESTION REDUCTION AND MULTI-OBJECTIVE OPTIMIZATION Hamid Shojaei Under the supervision of Professor Azadeh Davoodi At the University of Wisconsin-Madison The high volume and complexity of cells and interconnect structures are causing serious challenges to routability in modern VLSI design. Several new factors contribute to routing congestion including significantly-different wire size and spacing among the metal layers, sizes of inter-layer vias, various forms of routing blockages, local congestion due to pin density and wiring inside a global-cell, and virtual pins located at the higher metal layers. In addition, interconnects now play a significant role in impacting the performance metrics of a design including power, speed and area. Global routing, as the first stage in which the interconnects are planned, is now of significant importance in determining the performance metrics and the routability of the design. However, the standard model of global routing considers minimization of wirelength with a simplified model of routing resources which ignores these objectives and complicating factors. To address the above challenges, this dissertation has three contributions in rethinking global routing for modern VLSI design. First, we present a framework for congestion analysis for quick prediction of the locations of highly-utilized routing regions. The fast framework is suitable for integration in the design flow, for example as an integration within a routability-driven placement procedure. Second, we offer two contributions in order to estimate and manage the congestion caused by local nets which are ignored in a standard model of global routing. It allows optimizing congestion directly within global routing by treating global and detailed routing in a more holistic manner. In addition, many of the above-mentioned factors contributing to congestion are accounted for in our congestion analysis and optimization framework. Finally, we present a procedure for multi-objective global routing which is able to optimize multiple performance metrics beyond wirelength. The framework is a collaborative one which receives as input multiple global routing solutions created by single-objective procedures.

This book presents a novel multilevel full-chip router, namely mSIGMA for SIGnal-integrity and MAnufacturability optimization. These routing technologies will ensure faster time-to-market and time-to-profitability. The book includes a detailed description on the modern VLSI routing problems, and multilevel optimization on routing design to solve the chip complexity problem.

This volume provides a complete understanding of the fundamental causes of routing congestion in present-day and next-generation VLSI circuits, offers techniques for estimating and relieving congestion, and provides a critical analysis of the accuracy and effectiveness of these techniques. The book includes metrics and optimization techniques for routing congestion at various stages of the VLSI design flow. The subjects covered include an explanation of why the problem of congestion is important and how it will trend, plus definitions of metrics that are appropriate for measuring congestion, and descriptions of techniques for estimating and optimizing routing congestion issues in cell-/library-based VLSI circuits.

In the past two decades, research in VLSI physical design has been directed toward automation of layout process. Since the cost of fabricating a circuit is a fast growing function of the circuit area, circuit layout techniques are developed with an aim to produce layouts with small areas. Other criteria of optimality such as delay and via minimization need to be taken into consideration. This book includes 14 articles that deal with various stages of the VLSI layout problem. It covers topics including partitioning, floorplanning, placement, global routing, detailed routing and layout verification. Some of the chapters are review articles, giving the state-of-the-art of the problems related to timing driven placement, global and detailed routing, and circuit partitioning. The rest of the book contains research articles, giving recent findings of new approaches to the above-mentioned problems. They are all written by leading experts in the field. This book will serve as good references for both researchers and professionals who work in this field.

In the last few decades, multiscale algorithms have become a dominant trend in large-scale scientific computation. Researchers have successfully applied these methods to a wide range of simulation and optimization problems. This book gives a general overview of multiscale algorithms; applications to general combinatorial optimization problems such as graph partitioning and the traveling salesman problem; and VLSICAD applications, including circuit partitioning, placement, and VLSI routing. Additional chapters discuss optimization in reconfigurable computing, convergence in multilevel optimization, and model problems with PDE constraints. Audience: Written at the graduate level, the book is intended for engineers and mathematical and computational scientists studying large-scale optimization in electronic design automation.

This book originated from a workshop held at the DATE 2005 conference, namely Designing Complex SOCs. State-of-the-art in issues related to System-on-Chip (SoC) design by leading experts in the fields, it covers IP development, verification, integration, chip implementation, testing and software. It contains valuable academic and industrial examples for those involved with the design of complex SOCs.