Germanium is a semiconductor material that formed the basis for the development of transistor technology. Although the breakthrough of planar technology and integrated circuits put silicon in the foreground, in recent years there has been a renewed interest in germanium, which has been triggered by its strong potential for deep submicron (sub 45 nm) technologies. Germanium-Based technologies: From Materials to Devices is the first book to provide a broad, in-depth coverage of the field, including recent advances in Ge-technology and the fundamentals in material science, device physics and semiconductor processing. The contributing authors are international experts with a world-wide recognition and involved in the leading research in the field. The book also covers applications and the use of Ge for optoelectronics, detectors and solar cells. An ideal reference work for students and scientists working in the field of physics of semiconductor devices and materials, as well as for engineers in research centres and industry. Both the newcomer and the expert should benefit from this unique book. - State-of-the-art information available for the first time as an all-in-source - Extensive reference list making it an indispensable reference book - Broad coverage from fundamental aspects up to industrial applications

Due to the ever increasing electric fields in scaled CMOS devices, reliability is becoming a showstopper for further scaled technology nodes. Although several groups have already demonstrated functional Si channel devices with aggressively scaled Equivalent Oxide Thickness (EOT) down to 5Å, a 10 year reliable device operation cannot be guaranteed anymore due to severe Negative Bias Temperature Instability. This book focuses on the reliability of the novel (Si)Ge channel quantum well pMOSFET technology. This technology is being considered for possible implementation in next CMOS technology nodes, thanks to its benefit in terms of carrier mobility and device threshold voltage tuning. We observe that it also opens a degree of freedom for device reliability optimization. By properly tuning the device gate stack, sufficiently reliable ultra-thin EOT devices with a 10 years lifetime at operating conditions are demonstrated. The extensive experimental datasets collected on a variety of processed 300mm wafers and presented here show the reliability improvement to be process - and architecture-independent and, as such, readily transferable to advanced device architectures as Tri-Gate (finFET) devices. We propose a physical model to understand the intrinsically superior reliability of the MOS system consisting of a Ge-based channel and a SiO2/HfO2 dielectric stack. The improved reliability properties here discussed strongly support (Si)Ge technology as a clear frontrunner for future CMOS technology nodes.

This issue describes processing, materials and equipment for CMOS front-end integration including gate stack, source/drain and channel engineering. Topics: strained Si/SiGe and Si/SiGe on insulator; high-mobility channels including III-V¿s, etc.; nanowires and carbon nanotubes; high-k dielectrics, metal and FUSI gate electrodes; doping/annealing for ultra-shallow junctions; low-resistivity contacts; advanced deposition (e.g. ALD, CVD, MBE), RTP, UV, plasma and laser-assisted processes.

This book provides a comprehensive monograph on gate stacks in semiconductor technology. It covers the major latest developments and basics and will be useful as a reference work for researchers, engineers and graduate students alike. The reader will get a clear view of what has been done so far, what is the state-of-the-art and which are the main challenges ahead before we come any closer to a viable Ge and III-V MOS technology.

This book mainly focuses on reducing the high parasitic resistance in the source/drain of germanium nMOSFET. With adopting of the Implantation After Germanide (IAG) technique, P and Sb co-implantation technique and Multiple Implantation and Multiple Annealing (MIMA) technique, the electron Schottky barrier height of NiGe/Ge contact is modulated to 0.1eV, the thermal stability of NiGe is improved to 600°C and the contact resistivity of metal/n-Ge contact is drastically reduced to 3.8×10−7Ω•cm2, respectively. Besides, a reduced source/drain parasitic resistance is demonstrated in the fabricated Ge nMOSFET. Readers will find useful information about the source/drain engineering technique for high-performance CMOS devices at future technology node.

Currently strain engineering is the main technique used to enhance the performance of advanced silicon-based metal-oxide-semiconductor field-effect transistors (MOSFETs). Written from an engineering application standpoint, Strain-Engineered MOSFETs introduces promising strain techniques to fabricate strain-engineered MOSFETs and to methods to assess the applications of these techniques. The book provides the background and physical insight needed to understand new and future developments in the modeling and design of n- and p-MOSFETs at nanoscale. This book focuses on recent developments in strain-engineered MOSFETS implemented in high-mobility substrates such as, Ge, SiGe, strained-Si, ultrathin germanium-on-insulator platforms, combined with high-k insulators and metal-gate. It covers the materials aspects, principles, and design of advanced devices, fabrication, and applications. It also presents a full technology computer aided design (TCAD) methodology for strain-engineering in Si-CMOS technology involving data flow from process simulation to process variability simulation via device simulation and generation of SPICE process compact models for manufacturing for yield optimization. Microelectronics fabrication is facing serious challenges due to the introduction of new materials in manufacturing and fundamental limitations of nanoscale devices that result in increasing unpredictability in the characteristics of the devices. The down scaling of CMOS technologies has brought about the increased variability of key parameters affecting the performance of integrated circuits. This book provides a single text that combines coverage of the strain-engineered MOSFETS and their modeling using TCAD, making it a tool for process technology development and the design of strain-engineered MOSFETs.