This work was to establish whether it was possible to achieve a reasonable speedup by implementing FPGA based Hopfield neural networks for some simple constraint satisfaction problems. The results are significant - our initial implementation using standard Xilinx FPGAs yielded 2-3 orders of magnitude speedup over the Sun Blade 2000 workstation comes with 1.2-GHz version of the 64-bit UltraSPARC III Cu processor. The main problem with the work to date is that the problems are both unrealistically small and simplistic. That is the constraints on the N-Queen problem are simpler than those found in many real world scheduling applications. Thus, it is not clear whether we will be able to optimize the neuron structure for more complex problems since the weights matrix may not contain as many zero elements. Thus a new method for speed improvement of Hopfield neural networks for solving constraint satisfaction problems using Field Programmable Gate Arrays (FPGAs) was proposed and implemented.

During the 1980s and early 1990s there was signi?cant work in the design and implementation of hardware neurocomputers. Nevertheless, most of these efforts may be judged to have been unsuccessful: at no time have have ha- ware neurocomputers been in wide use. This lack of success may be largely attributed to the fact that earlier work was almost entirely aimed at developing custom neurocomputers, based on ASIC technology, but for such niche - eas this technology was never suf?ciently developed or competitive enough to justify large-scale adoption. On the other hand, gate-arrays of the period m- tioned were never large enough nor fast enough for serious arti?cial-neur- network (ANN) applications. But technology has now improved: the capacity and performance of current FPGAs are such that they present a much more realistic alternative. Consequently neurocomputers based on FPGAs are now a much more practical proposition than they have been in the past. This book summarizes some work towards this goal and consists of 12 papers that were selected, after review, from a number of submissions. The book is nominally divided into three parts: Chapters 1 through 4 deal with foundational issues; Chapters 5 through 11 deal with a variety of implementations; and Chapter 12 looks at the lessons learned from a large-scale project and also reconsiders design issues in light of current and future technology.

In contrast with analog design, digital design and implementation of any logic circuit suffer much from the difficulty in terms of economy and implementation. Neural networks are artificial systems inspired by the brain's cognitive behavior, which can learn tasks with some degree of complexity, such as, optimization problems, text and speech recognition. Since the topology of neural networks is highly crucial to the performance, the reconfigurable ability of the neural network hardware is very essential. Reconfigurability factually means several different designs can be implemented on a single architecture. Therefore, this work proposes an efficient architecture to implement the reconfigurable back propagation and Hopfield neural networks. We specifically adopted the reconfigurable artificial neural networks approach to show how it is possible to build an efficient chip. Simple neural network models with an appropriate training were used to behave as traditional logic functions in the bit- level. In order to further reduce the hardware, memories-sharing method has been adopted. Also, a comparison between the proposed and traditional networks shows that the proposed network has significantly reduced the time delay and power consumption. Xilinx - ISE is used to synthesize our design. VHDL code is used to build the architecture. The architecture code is then downloaded to FPGAs (Field Programmable Gate Array) to implement the design. FPGAs are strong tools to implement ANNs as one can exploit concurrency and rapidly reconfigure to adapt the weights and topologies of an ANN. Also, XPower, as one of the best tools in Xilinx, was used to measure the total required power by our architecture. Finally, the results showed that the proposed reconfigurable architecture leads to a considerable decrease in the consumed power to almost 43% as well as the total time delay. Also, the architecture can easily be scalable as a future work and is able to cope with several network sizes with the same hardware.

We present in this volume the collection of finally accepted papers of the eighth edition of the “IWANN” conference (“International Work-Conference on Artificial Neural Networks”). This biennial meeting focuses on the foundations, theory, models and applications of systems inspired by nature (neural networks, fuzzy logic and evolutionary systems). Since the first edition of IWANN in Granada (LNCS 540, 1991), the Artificial Neural Network (ANN) community, and the domain itself, have matured and evolved. Under the ANN banner we find a very heterogeneous scenario with a main interest and objective: to better understand nature and beings for the correct elaboration of theories, models and new algorithms. For scientists, engineers and professionals working in the area, this is a very good way to get solid and competitive applications. We are facing a real revolution with the emergence of embedded intelligence in many artificial systems (systems covering diverse fields: industry, domotics, leisure, healthcare, ... ). So we are convinced that an enormous amount of work must be, and should be, still done. Many pieces of the puzzle must be built and placed into their proper positions, offering us new and solid theories and models (necessary tools) for the application and praxis of these current paradigms. The above-mentioned concepts were the main reason for the subtitle of the IWANN 2005 edition: “Computational Intelligence and Bioinspired Systems.” The call for papers was launched several months ago, addressing the following topics: 1. Mathematical and theoretical methods in computational intelligence.