With spacecraft designs placing more emphasis on reduced cost, faster design time, and higher performance, it is easy to understand why more commercial-off-the-shelf (COTS) devices are being used in space based applications. The COTS devices offer spacecraft designers shorter design-to- orbit times, lower system costs, orders of magnitude better performance, and a much better software availability than their radiation hardened (radhard) counterparts. The major drawback to using COTS devices in space is their increased susceptibility to the effects of radiation, single event upsets (SEUs) in particular. This thesis will focus on the implementation of a fault tolerant computer system. The hardware design presented here has two different benefits. First, the system can act as a software testbed, which allows testing of software fault tolerant techniques in the presence of radiation induced SEUs. This allows the testing of the software algorithms in the environment they were designed to operate in without the expense of being placed in orbit. Additionally, the design can be used as a hybrid fault tolerant computer system. By combining the masking ability of the hardware with supporting software, the system can mask out and reset processor errors in real time. The design layout will be presented using OrCAD schematics.

Operating computers in space requires the use of very expensive radiation hardened microelectronics devices. Unfortunately, the United States radiation hardened market is rapidly shrinking and makes up a very small percentage of the commercial market. For these reasons, and the fact that commercial-off-the-shelf (COTS) devices are cheaper, more capable, readily available, and software availability is much greater, the use of COTS devices in future space systems is fast becoming a reality. A significant disadvantage of COTS devices is their susceptibility to radiation induced single event upsets (SEUs), among other radiation effects which are detrimental to electronic systems. This thesis focuses on the board level design of a tool which enables the analysis of fault tolerant computing techniques in a laboratory environment in the presence of radiation induced SEUs. When implemented, this tool will be beneficial to the study of using COTS devices in space. The tool will provide the capability to analyze the performance of hardware redundancy techniques and software algorithms intended to improve the performance of COTS microprocessors in this environment prior to their use in designs intended for actual space applications. Cadence Concept(TM) design schematics, associated Verilog(registered) code and simulation results are presented to develop this concept.

Operating computers in space requires the use of very expensive radiation hardened microelectronics devices. Unfortunately, the United States radiation hardened market is rapidly shrinking and makes up a very small percentage of the commercial market. For these reasons, and the fact that commercial-off-the-shelf (COTS) devices are cheaper, more capable, readily available, and software availability is much greater, the use of COTS devices in future space systems is fast becoming a reality. A significant disadvantage of COTS devices is their susceptibility to radiation induced single event upsets (SEUs), among other radiation effects which are detrimental to electronic systems. This thesis focuses on the board level design of a tool which enables the analysis of fault tolerant computing techniques in a laboratory environment in the presence of radiation induced SEUs. When implemented, this tool will be beneficial to the study of using COTS devices in space. The tool will provide the capability to analyze the performance of hardware redundancy techniques and software algorithms intended to improve the performance of COTS microprocessors in this environment prior to their use in designs intended for actual space applications. Cadence Concept(TM) design schematics, associated Verilog(registered) code and simulation results are presented to develop this concept.

For the editors of this book, as well as for many other researchers in the area of fault-tolerant computing, Dr. William Caswell Carter is one of the key figures in the formation and development of this important field. We felt that the IFIP Working Group 10.4 at Baden, Austria, in June 1986, which coincided with an important step in Bill's career, was an appropriate occasion to honor Bill's contributions and achievements by organizing a one day "Symposium on the Evolution of Fault-Tolerant Computing" in the honor of William C. Carter. The Symposium, held on June 30, 1986, brought together a group of eminent scientists from all over the world to discuss the evolu tion, the state of the art, and the future perspectives of the field of fault-tolerant computing. Historic developments in academia and industry were presented by individuals who themselves have actively been involved in bringing them about. The Symposium proved to be a unique historic event and these Proceedings, which contain the final versions of the papers presented at Baden, are an authentic reference document.

Abstract: "With parallel machines increasingly taking on critical and complex applications, it is important to make them dependable to ensure their commercial success. Fault-tolerance in the network to accommodate link and node failures is an important step towards this goal. This can be achieved by employing cost-effective fault-tolerant algorithms. However, despite substantial efforts on the theoretical front in developing fault-tolerant routing techniques and architectures, these ideas have not manifested themselves in many commercial platforms. The ramifications of providing fault-tolerant routing in terms of cost and performance is still not clear to the computer architect. Such an insight can only be gained through detailed analysis of a design with realistic workloads. Since no current evaluation platform supports this, previous research on fault-tolerant routing has used synthetic workloads for analyzing performance. This paper presents a comprehensive evaluation testbed for interconnection networks and routing algorithms using real applications. The testbed is flexible enough to implement any network topology and fault-tolerant routing algorithm, and allows the system architect to study the cost versus performance tradeoffs for a range of network parameters. We illustrate its use with one fault-tolerant algorithm and analyze the performance of four shared memory applications with different fault conditions. We also show how the testbed can be used to drive future research in fault-tolerant routing algorithms and architectures, by proposing and evaluating novel architectural enhancements to the network router, called path selection heuristics (PSH). We propose three such schemes and the Least Recently Used (LRU) PSH is shown to give the best performance in the presence of faults."