ABSTRACT: While previously studying the design of a built-in current (BIC) sensor that made use of the charge quantization approach for detecting i[subscript DDT], a new sensor has been developed which makes use of the parasitic resistance that exists between the core of an integrated circuit and its power pads. The voltage drop that develops across the parasitic metal resistance through the i[subscript DDT] switching activity of the SRAM has been successfully amplified to distinguish between single and multiple cell switching. Pattern sensitivity faults have been effectively modeled and successfully detected making use of the i[subscript DDT] sensor proposed in this work.

ABSTRACT: In very deep submicron technologies, supply current testing techniques are essential to achieve high fault coverage and to reduce test length. Due to high supply leakage currents, the quiescent power supply current (IDDQ) testing technique is no longer applicable for deep submicron technologies. However, the transient power supply current (IDDT) testing technique can be used in an environment of high leakage current and offers high fault coverage and reduced test time. A new built-in current sensor is presented here that has the potential to overcome some of the limitations of the other current sensors proposed previously. The current sensor can find application for testing embedded static random access memories (SRAMs) at high frequencies. It employs a high pass filter circuit to eliminate the effects of leakage current and utilizes cascaded high bandwidth amplifiers for high IDDT measurement sensitivity. Open defects in SRAMs are modeled as resistive open defects and studied using the new built-in current sensor for a 0.35 [(mu symbol)m] process technology. The current sensor efficiently detects the open defects in SRAMs that cause transition faults and destructive read-out faults. A two-vector test pattern is suggested with the current sensor for the detection of these faults. The first test vector is used to initialize the SRAM memory cell being tested, and the second test vector is applied to activate the fault.