Digital Timing Macromodeling for VLSI Design Verification first of all provides an extensive history of the development of simulation techniques. It presents detailed discussion of the various techniques implemented in circuit, timing, fast-timing, switch-level timing, switch-level, and gate-level simulation. It also discusses mixed-mode simulation and interconnection analysis methods. The review in Chapter 2 gives an understanding of the advantages and disadvantages of the many techniques applied in modern digital macromodels. The book also presents a wide variety of techniques for performing nonlinear macromodeling of digital MOS subcircuits which address a large number of shortcomings in existing digital MOS macromodels. Specifically, the techniques address the device model detail, transistor coupling capacitance, effective channel length modulation, series transistor reduction, effective transconductance, input terminal dependence, gate parasitic capacitance, the body effect, the impact of parasitic RC-interconnects, and the effect of transmission gates. The techniques address major sources of errors in existing macromodeling techniques, which must be addressed if macromodeling is to be accepted in commercial CAD tools by chip designers. The techniques presented in Chapters 4-6 can be implemented in other macromodels, and are demonstrated using the macromodel presented in Chapter 3. The new techniques are validated over an extremely wide range of operating conditions: much wider than has been presented for previous macromodels, thus demonstrating the wide range of applicability of these techniques.

The purpose of this research is to develop a cost effective timing simulator for digital metal-oxide semiconductor (MOS) very large scale integrated (VLSI) circuits. Verification of the correct operation of VLSI circuits is a very costly process. Therefore, the development of faster verification tools is very important. Fast timing simulation attempts to extract information comparable to that of circuit simulation while requiring processing time comparable to that of logic simulation. This goal is achieved by the use of a nonlinear macromodeling which applies simple voltage calculations with accurate results. Macromodel current equations have been derived based on the dc characteristic equations of MOS transistors, capacitive loading effects, and model card parameters. The voltage-time equations remain relatively simple, although many transistor parameters are included. The equations are used to relate the time response of dc-connected subcircuits to the physical parameters of the devices and their interconnection and take into account the input slew rate and loading. The equations have been implemented in a simulator which produces accurate results and is up to three orders of magnitude faster than SPICE2. The application of these techniques to automatic mixed-mode simulation and parallel processing has also been investigated.

The basic goals of the research presented in this thesis are to remove various shortcomings in existing fast timing simulators and to extend the scope and applicability of fast timing simulation to submicron digital circuits. Existing fast timing simulators have been shown to be extremely efficient in simulating large digital circuits compared to classical electrical-level simulators. However, these simulators have a number of accuracy-related problems: inaccurate MOS modeling, inadequate consideration of the effects of internal nodes in complex logic gates and of interconnect loading, etc. The thrust of this dissertation is in the investigation of techniques that will allow us to remove these shortcomings while preserving, as much as possible, the simulation efficiency. To this end, a regionwise quadratic (RWQ) modeling technique that allows arbitrary MOS drain current models to be used in fast timing simulation applications has been developed. This technique considerably improves the accuracy of the models and the simulation results, while retaining the characteristics of the macromodels that enable fast and efficient solution techniques to be applied. The issue of internal nodes in complex logic gates is addressed and a technique based on waveform relaxation that enables these internal nodes to be simulated accurately has been developed. This method is applicable to circuits exhibiting complex interactions between multiple circuit nodes as well as to circuits in which internal nodes are inputs to subsequent logic stages. A novel and accurate effective capacitance calculation technique to account for the effect of interconnects on nonlinear driver gates is proposed. This technique accurately predicts the delays and shapes of driver output waveforms under interconnect loading without adding any computational overhead. A novel method for incremental fast timing simulation and transient sensitivity analysis is also described. It is shown that in applications requiring a large number of closely related transient analyses, the incremental simulation technique can provide accurate results with a substantial reduction in computational cost. Finally, an application of the fast timing simulation technique to the simulation of transient faults is discussed. The methodologies and techniques developed in this thesis have been implemented in a fast timing simulator called ILLIADS2. The application of ILLIADS2 on a number of MOS circuits is demonstrated.

Only two decades ago most electronic circuits were designed with a slide-rule, and the designs were verified using breadboard techniques. Simulation tools were a research curiosity and in general were mistrusted by most designers and test engineers. In those days the programs were not user friendly, models were inadequate, and the algorithms were not very robust. The demand for simulation tools has been driven by the increasing complexity of integrated circuits and systems, and it has been aided by the rapid decrease in the cost of com puting that has occurred over the past several decades. Today a wide range of tools exist for analYSiS, deSign, and verification, and expert systems and synthesis tools are rapidly emerging. In this book only one aspect of the analysis and design process is examined. but it is a very important aspect that has received much attention over the years. It is the problem of accurate circuit and timing simulation.