This book describes the design of switched-capacitor filter circuits using low gain amplifiers and demonstrates some techniques that can minimize the effects of parasitic capacitances during the design phase. Focus is given in the design of low-pass and band-pass SC filters, and how higher order filters can be achieved using cascaded biquadratic filter sections. The authors also describe a low voltage implementation of a low-pass SC filter.

This book discusses the design of switched-capacitor filters in deep-submicron CMOS technologies. The authors describe several topologies for switched-capacitor filter circuits that do not require high-gain high-bandwidth amplifiers. Readers will also learn two analysis methodologies that can be implemented efficiently in software and integrated into optimization environments for the automation of design for switched-capacitor filters. Although the optimization examples discussed utilize low gain amplifiers, the demonstrated methodologies can also be used for conventional, high-gain high-bandwidth amplifiers.

The purpose of this book is to present analysis and design principles, procedures and techniques of analog integrated circuits which are to be implemented in MOS (metal oxide semiconductor) technology. MOS technology is becoming dominant in the realization of digital systems, and its use for analog circuits opens new pos sibilities for the design of complex mixed analog/digital VLSI (very large scale in tegration) chips. Although we are focusing attention in this book principally on circuits and systems which can be implemented in CMOS technology, many con siderations and structures are of a general nature and can be adapted to other promising and emerging technologies, namely GaAs (Gallium Arsenide) and BI MOS (bipolar MOS, i. e. circuits which combine both bipolar and CMOS devices) technology. Moreover, some of the structures and circuits described in this book can also be useful without integration. In this book we describe two large classes of analog integrated circuits: • switched capacitor (SC) networks, • continuous-time CMOS (unswitched) circuits. SC networks are sampled-data systems in which electric charges are transferred from one point to another at regular discrete intervals of time and thus the signal samples are stored and processed. Other circuits belonging to this class of sampled-data systems are charge transfer devices (CTD) and charge coupled dev ices (CCD). In contrast to SC circuits, continuous-time CMOS circuits operate continuously in time. They can be considered as subcircuits or building blocks (e. g.

Design of Very High-Frequency Multirate Switched-Capacitor Circuits presents the theory and the corresponding CMOS implementation of the novel multirate sampled-data analog interpolation technique which has its great potential on very high-frequency analog frond-end filtering due to its inherent dual advantage of reducing the speed of data-converters and DSP core together with the specification relaxation of the post continuous-time filtering. This technique completely eliminates the traditional phenomenon of sampled-and-hold frequency-shaping at the lower input sampling rate. Also, in order to tackle physical IC imperfections at very high frequency, the state-of-the-art circuit design and layout techniques for high-speed Switched-Capacitor (SC) circuits are comprehensively discussed: -Optimum circuit architecture tradeoff analysis -Simple speed and power trade-off analysis of active elements -High-order filtering response accuracy with respect to capacitor-ratio mismatches -Time-interleaved effect with respect to gain and offset mismatch -Time-interleaved effect with respect to timing-skew and random jitter with non-uniformly holding -Stage noise analysis and allocation scheme -Substrate and supply noise reduction -Gain-and offset-compensation techniques -High-bandwidth low-power amplifier design and layout -Very low timing-skew multiphase generation Two tailor-made optimum design examples in CMOS are presented. The first one achieves a 3-stage 8-fold SC interpolating filter with 5.5MHz bandwidth and 108MHz output sampling rate for a NTSC/PAL CCIR 601 digital video at 3 V. Another is a 15-tap 57MHz SC FIR bandpass interpolating filter with 4-fold sampling rate increase to 320MHz and the first-time embedded frequency band up-translation for DDFS system at 2.5V. The corresponding chip prototype achieves so far the highest operating frequency, highest filter order and highest center frequency with highest dynamic range under the lowest supply voltage when compared to the previously reported high-frequency SC filters in CMOS.

The Principles and Application in Engineering Series is a new series of convenient, economical references sharply focused on particular engineering topics and subspecialties. Each volume in this series comprises chapters carefully selected from CRC's bestselling handbooks, logically organized for optimum convenience, and thoughtfully priced to fit

With the fast advancement of CMOS fabrication technology, more and more signal-processing functions are implemented in the digital domain for a lower cost, lower power consumption, higher yield, and higher re-configurability. This has recently generated a great demand for low-power, low-voltage A/D converters that can be realized in a mainstream deep-submicron CMOS technology. However, the discrepancies between lithography wavelengths and circuit feature sizes are increasing. Lower power supply voltages significantly reduce noise margins and increase variations in process, device and design parameters. Consequently, it is steadily more difficult to control the fabrication process precisely enough to maintain uniformity. The inherent randomness of materials used in fabrication at nanoscopic scales means that performance will be increasingly variable, not only from die-to-die but also within each individual die. Parametric variability will be compounded by degradation in nanoscale integrated circuits resulting in instability of parameters over time, eventually leading to the development of faults. Process variation cannot be solved by improving manufacturing tolerances; variability must be reduced by new device technology or managed by design in order for scaling to continue. Similarly, within-die performance variation also imposes new challenges for test methods. In an attempt to address these issues, Low-Power High-Resolution Analog-to-Digital Converters specifically focus on: i) improving the power efficiency for the high-speed, and low spurious spectral A/D conversion performance by exploring the potential of low-voltage analog design and calibration techniques, respectively, and ii) development of circuit techniques and algorithms to enhance testing and debugging potential to detect errors dynamically, to isolate and confine faults, and to recover errors continuously. The feasibility of the described methods has been verified by measurements from the silicon prototypes fabricated in standard 180nm, 90nm and 65nm CMOS technology.

This book constitutes the refereed proceedings of the 5th IFIP WG 5.5/SOCOLNET Doctoral Conference on Computing, Electrical and Industrial Systems, DoCEIS 2014, held in Costa de Caparica, Portugal, in April 2014. The 68 revised full papers were carefully reviewed and selected from numerous submissions. They cover a wide spectrum of topics ranging from collaborative enterprise networks to microelectronics. The papers are organized in the following topical sections: collaborative networks; computational systems; self-organizing manufacturing systems; monitoring and supervision systems; advances in manufacturing; human-computer interfaces; robotics and mechatronics, Petri nets; multi-energy systems; monitoring and control in energy; modelling and simulation in energy; optimization issues in energy; operation issues in energy; power conversion; telecommunications; electronics: design; electronics: RF applications; and electronics: devices.