Wafer Scale Integration (WSI) is the culmination of the quest for larger integrated circuits. In VLSI chips are developed by fabricating a wafer with hundreds of identical circuits, testing the circuits, dicing the wafer, and packaging the good dice. In contrast in WSI, a wafer is fabricated with several types of circuits (generally referred to as cells), with multiple instances of each cell type, the cells are tested, and good cells are interconnected to realize a system on the wafer. Since most signal lines stay on the wafer, stray capacitance is low, so that high speeds are achieved with low power consumption. For the same technology a WSI implementation may be a factor of five faster, dissipate a factor of ten less power, and require one hundredth to one thousandth the volume. Successful development of WSI involves many overlapping disciplines, ranging from architecture to test design to fabrication (including laser linking and cutting, multiple levels of interconnection, and packaging). This book concentrates on the areas that are unique to WSI and that are as a result not well covered by any of the many books on VLSI design. A unique aspect of WSI is that the finished circuits are so large that there will be defects in some portions of the circuit. Accordingly much attention must be devoted to designing architectures that facilitate fault detection and reconfiguration to of WSI include fabrication circumvent the faults. Other unique aspects technology and packaging.

A practical understanding of these concepts and their application can help to reduce the chance of having device failures.

The proceedings of the Second IEEE Symposium on title], held in Dallas, December 1990, comprise 143 papers on topics in algorithm, task scheduling, networks, operating systems, databases, architecture, fault tolerance, VLSI design, graphis/image processing, artificial intelligence, languages/compil