The number of gates on a chip is quickly growing toward and beyond the one billion mark. Keeping all the gates running at the beat of a single or a few rationally related clocks is becoming impossible. In static timing analysis process variations and signal integrity issues stretch the timing margins to the point where they become too conservative and result in significant overdesign. Importance and difficulty of such problems push some developers to once again turn to asynchronous alternatives. However, the electronics industry for the most part is still reluctant to adopt asynchronous design (with a few notable exceptions) due to a common belief that we still lack a commercial-quality Electronic Design Automation tools (similar to the synchronous RTL-to-GDSII flow) for asynchronous circuits. The purpose of this paper is to counteract this view by presenting design flows that can tackle large designs without significant changes with respect to synchronous design flow. We are limiting ourselves to four design flows that we believe to be closest to this goal. We start from the Tangram flow, because it is the most commercially proven and it is one of the oldest from a methodological point of view. The other three flows (Null Convention Logic, de-synchronization, and gate-level pipelining) could be considered together as asynchronous re-implementations of synchronous (RTL- or gate-level) specifications. The main common idea is substituting the global clocks by local synchronizations. Their most important aspect is to open the possibility to implement large legacy synchronous designs in an almost "push button" manner, where all asynchronous machinery is hidden, so that synchronous RTL designers do not need to be re-educated. These three flows offer a trade-off from very low overhead, almost synchronous implementations, to very high performance, extremely robust dual-rail pipelines.

Principles of Asynchronous Circuit Design - A Systems Perspective addresses the need for an introductory text on asynchronous circuit design. Part I is an 8-chapter tutorial which addresses the most important issues for the beginner, including how to think about asynchronous systems. Part II is a 4-chapter introduction to Balsa, a freely-available synthesis system for asynchronous circuits which will enable the reader to get hands-on experience of designing high-level asynchronous systems. Part III offers a number of examples of state-of-the-art asynchronous systems to illustrate what can be built using asynchronous techniques. The examples range from a complete commercial smart card chip to complex microprocessors. The objective in writing this book has been to enable industrial designers with a background in conventional (clocked) design to be able to understand asynchronous design sufficiently to assess what it has to offer and whether it might be advantageous in their next design task.

This book constitutes the thoroughly refereed post-conference proceedings of 18th International Workshop on Power and Timing Modeling, Optimization and Simulation, PATMOS 2008, featuring Integrated Circuit and System Design, held in Lisbon, Portugal during September 10-12, 2008. The 31 revised full papers and 10 revised poster papers presented together with 3 invited talks and 4 papers from a special session on reconfigurable architectures were carefully reviewed and selected from numerous submissions. The papers are organized in topical sections on low-leakage and subthreshold circuits, low-power methods and models, arithmetic and memories, variability and statistical timing, synchronization and interconnect, power supplies and switching noise, low-power circuits; reconfigurable architectures, circuits and methods, power and delay modeling, as well as power optimizations addressing reconfigurable architectures.

In recent years, both Networks-on-Chip, as an architectural solution for high-speed interconnect, and power consumption, as a key design constraint, have continued to gain interest in the design and research communities. This book offers a single-source reference to some of the most important design techniques proposed in the context of low-power design for networks-on-chip architectures.

This book constitutes the refereed proceedings of the 8th International Workshop on Cryptographic Hardware and Embedded Systems, CHES 2006, held in Yokohama, Japan in October 2006. The 32 revised full papers presented together with three invited talks were carefully reviewed and selected from 112 submissions.

The two-volume set originates from the Advanced Course on Petri Nets held in Dagstuhl, Germany in September 1996; beyond the lectures given there, additional chapters have been commissioned to give a well-balanced presentation of the state of the art in the area. Together with its companion volume "Lectures on Petri Nets I: Basic Models" this book is the actual reference for the area and addresses professionals, students, lecturers, and researchers who are - interested in systems design and would like to learn to use Petri nets familiar with subareas of the theory or its applications and wish to view the whole area - interested in learning about recent results presented within a unified framework - planning to apply Petri nets in practical situations - interested in the relationship of Petri nets to other models of concurrent systems.

The first of two volumes in the Electronic Design Automation for Integrated Circuits Handbook, Second Edition, Electronic Design Automation for IC System Design, Verification, and Testing thoroughly examines system-level design, microarchitectural design, logic verification, and testing. Chapters contributed by leading experts authoritatively discuss processor modeling and design tools, using performance metrics to select microprocessor cores for integrated circuit (IC) designs, design and verification languages, digital simulation, hardware acceleration and emulation, and much more. New to This Edition: Major updates appearing in the initial phases of the design flow, where the level of abstraction keeps rising to support more functionality with lower non-recurring engineering (NRE) costs Significant revisions reflected in the final phases of the design flow, where the complexity due to smaller and smaller geometries is compounded by the slow progress of shorter wavelength lithography New coverage of cutting-edge applications and approaches realized in the decade since publication of the previous edition—these are illustrated by new chapters on high-level synthesis, system-on-chip (SoC) block-based design, and back-annotating system-level models Offering improved depth and modernity, Electronic Design Automation for IC System Design, Verification, and Testing provides a valuable, state-of-the-art reference for electronic design automation (EDA) students, researchers, and professionals.