Abstract: "We present the methods used in the implementation of an incremental zero/unit-delay switch-level logic simulator for MOS circuits based on the MOSSIM II switch-level model. The incremental simulator is embedded within a single fully-integrated capture/compile/simulate tool. Modifications to the design at any level in the structural design hierarchy are automatically mapped into changes in the underlying transistor netlist and the incremental simulator is triggered to quickly resimulate only those regions of the circuit whose behavior has been modified by the change."

Only two decades ago most electronic circuits were designed with a slide-rule, and the designs were verified using breadboard techniques. Simulation tools were a research curiosity and in general were mistrusted by most designers and test engineers. In those days the programs were not user friendly, models were inadequate, and the algorithms were not very robust. The demand for simulation tools has been driven by the increasing complexity of integrated circuits and systems, and it has been aided by the rapid decrease in the cost of com puting that has occurred over the past several decades. Today a wide range of tools exist for analYSiS, deSign, and verification, and expert systems and synthesis tools are rapidly emerging. In this book only one aspect of the analysis and design process is examined. but it is a very important aspect that has received much attention over the years. It is the problem of accurate circuit and timing simulation.