A key component in a new high-speed prototype network, called the Multiple Crossbar Network (MCN) being developed at Los Alamos National Laboratory, is a crossbar switching core and its controller. This switching core allows for up to 32 (800 Mbit/second) connections to pass through it simultaneously. The motivation for this network is to allow visualization data to be sent at movie rate speeds to a users workstation from a supercomputer. This paper reviews the key concepts and components of the MCN, and then focuses on the behavioral level design of a distributed asynchronous VLSI controller chip set for the switching core. A unique design methodology is presented and then applied to the controller which uses an externally distributed chip set, and distributed asynchronous finite state machines internally.

Foreword -- Foreword to the First Printing -- Preface -- Chapter 1 -- Introduction -- Chapter 2 -- Message Switching Layer -- Chapter 3 -- Deadlock, Livelock, and Starvation -- Chapter 4 -- Routing Algorithms -- Chapter 5 -- CollectiveCommunicationSupport -- Chapter 6 -- Fault-Tolerant Routing -- Chapter 7 -- Network Architectures -- Chapter 8 -- Messaging Layer Software -- Chapter 9 -- Performance Evaluation -- Appendix A -- Formal Definitions for Deadlock Avoidance -- Appendix B -- Acronyms -- References -- Index.