The main goal of this book is to review at the nano and atomic scale the very complex scientific issues that pertain to the use of advanced high dielectric constant (high-k) materials in next generation semiconductor devices. One of the key obstacles to integrate this novel class of materials into Si nano-technology are the electronic defects in high-k dielectrics. It has been established that defects do exist in high-k dielectrics and they play an important role in device operation. The unique feature of this book is a special focus on the important issue of defects. The subject is covered from various angles, including silicon technology, processing aspects, materials properties, electrical defects, microstructural studies, and theory. The authors who have contributed to the book represents a diverse group of leading scientists from academic, industrial and governmental labs worldwide who bring a broad array of backgrounds (basic and applied physics, chemistry, electrical engineering, surface science, and materials science). The contributions to this book are accessible to both expert scientists and engineers who need to keep up with leading edge research, and newcomers to the field who wish to learn more about the exciting basic and applied research issues relevant to next generation device technology.

The goal of this NATO Advanced Research Workshop (ARW) entitled “Defects in Advanced High-k Dielectric Nano-electronic Semiconductor Devices”, which was held in St. Petersburg, Russia, from July 11 to 14, 2005, was to examine the very complex scientific issues that pertain to the use of advanced high dielectric constant (high-k) materials in next generation semiconductor devices. The special feature of this workshop was focus on an important issue of defects in this novel class of materials. One of the key obstacles to high-k integration into Si nano-technology are the electronic defects in high-k materials. It has been established that defects do exist in high-k dielectrics and they play an important role in device operation. However, very little is known about the nature of the defects or about possible techniques to eliminate, or at least minimize them. Given the absence of a feasible alternative in the near future, well-focused scientific research and aggressive development programs on high-k gate dielectrics and related devices must continue for semiconductor electronics to remain a competitive income producing force in the global market.

This issue covers in detail all aspects of the physics and the technology of high dielectric constant gate stacks, including high mobility substrates, high dielectric constant materials, processing, metals for gate electrodes, interfaces, physical, chemical, and electrical characterization, gate stack reliability, and DRAM and non-volatile memories.

The drive toward smaller and smaller electronic componentry has huge implications for the materials currently being used. As quantum mechanical effects begin to dominate, conventional materials will be unable to function at scales much smaller than those in current use. For this reason, new materials with higher electrical permittivity will be requ

The issue covers in detail all aspects of the physics and the technology of high dielectric constant gate stacks, including high mobility substrates, novel and still higher permittivity dielectric materials, CMOS processing with high-K layers, metals for gate electrodes, interface issues, physical, chemical, and electrical characterization, gate stack reliability, and DRAM and non-volatile memories.

This issue covers, in detail, all aspects of the physics and the technology of high dielectric constant gate stacks, including high mobility substrates, high dielectric constant materials, processing, metals for gate electrodes, interfaces, physical, chemical, and electrical characterization, gate stack reliability, and DRAM and non-volatile memories.