Flash memories have become the main type of non-volatile memories. They are widely used in mobile, embedded and mass-storage devices. Flash memories store data in floating-gate cells, where the amount of charge stored in cells 0́3 called cell levels 0́3 is used to represent data. To reduce the level of any cell, a whole cell block (about 106 cells) must be erased together and then reprogrammed. This operation, called block erasure, is very costly and brings significant challenges to cell programming and rewriting of data. To address these challenges, rank modulation and rewriting codes have been proposed for reliably storing and modifying data. However, for these new schemes, many problems still remain open. In this work, we study error-correcting rank-modulation codes and rewriting codes for flash memories. For the rank modulation scheme, we study a family of one- error-correcting codes, and present efficient encoding and decoding algorithms. For rewriting, we study a family of linear write-once memory (WOM) codes, and present an effective algorithm for rewriting using the codes. We analyze the performance of our solutions for both schemes.

Nowadays it is hard to find an electronic device which does not use codes: for example, we listen to music via heavily encoded audio CD's and we watch movies via encoded DVD's. There is at least one area where the use of encoding/decoding is not so developed, yet: Flash non-volatile memories. Flash memory high-density, low power, cost effectiveness, and scalable design make it an ideal choice to fuel the explosion of multimedia products, like USB keys, MP3 players, digital cameras and solid-state disk. In ECC for Non-Volatile Memories the authors expose the basics of coding theory needed to understand the application to memories, as well as the relevant design topics, with reference to both NOR and NAND Flash architectures. A collection of software routines is also included for better understanding. The authors form a research group (now at Qimonda) which is the typical example of a fruitful collaboration between mathematicians and engineers.

Flash memories are, by far, the most important type of non-volatile memory in use today. They are employed widely in mobile, embedded, and mass-storage applications, and the growth in this sector continues at a staggering pace. Moreover, since flash memories do not suffer from the mechanical limitations of magnetic disk drives, solid-state drives have the potential to upstage the magnetic recording industry in the foreseeable future. The research goal of this dissertation is the discovery of new coding theory methods that supports efficient design of flash memories. Flash memory is comprised of blocks of cells, wherein each cell can take on q>̲ 2 levels. While increasing the cell level is easy, reducing its level can be accomplished only by erasing an entire block. Such block erasures are not only time-consuming, but also degrade the memory lifetime. Our main contribution in this research is the design of rewriting codes that maximize the number of times that information can be written prior to incurring a block erasure. Examples of such coding schemes are flash/floating codes and buffer codes, introduced by Jiang and Bruck et al. in 2007, and WOM-codes that were presented by Rivest and Shamir almost three decades ago. The overall goal in these codes is to maximize the amount of information written to a fixed number of cells in a fixed number of writes. Furthermore, the design of error-correcting codes in flash memories is extensively studied. It is shown how to modify WOM-codes to support an error-correction capability. Motivated by the asymmetry of the error behavior of flash memories and the work by Cassuto et al., a coding scheme to correct asymmetric errors is presented. An extensive empirical database of errors was used to develop a comprehensive understanding of the error behavior as well as to design specific error-correcting codes for flash memories. This research on flash memories is expanded to other directions. Wear leveling techniques are widely used in flash memories in order to reduce and balance block erasures. It is shown that coding schemes to be used in these techniques can significantly reduce the number block erasures incurred during data movement. Also, the design of parallel cell programming algorithms is studied for the specific constraints and behavior of flash cells.

In 1999, a conference called International Meeting on Coding Theory and Cryptography took place at Mota Castle in Castilia (Spain). The conference had great acceptance within the community of coding theory and cryptography researchers. At that moment, and also nowadays, there are not many international workshops about these topics, at least if we compare with other mathematical and engineering subjects of research. Therefore, the general desire was to continue with more Castle Meetings. However, the following conference did not take place until 2008. In that case, the conference was called II International Castle Meeting on Coding Theory and Applications allowing more topics related to coding theory apart from cryptography. Such conference took place at Mota Castle again and the number of participants was similar to the previous edition. The present edition of the conference, called III International Castle Meeting on Coding Theory and Applications has been held at Cardona Castle in Catalonia (Spain). The number of communications has increased and a number of selected papers will be published in a special issue of the journal Designs, Codes and Cryptography. As in the previous editions, the conference has been of high level with notorious invited speakers and scientic committee members.

Mohammed Rajab proposes different technologies like the error correction coding (ECC), sources coding and offset calibration that aim to improve the reliability of the NAND flash memory with low implementation costs for industrial application. The author examines different ECC schemes based on concatenated codes like generalized concatenated codes (GCC) which are applicable for NAND flash memories by using the hard and soft input decoding. Furthermore, different data compression schemes are examined in order to reduce the write amplification effect and also to improve the error correct capability of the ECC by combining both schemes.

The book presents several advances in different research areas related to data storage, from the design of a hierarchical memory subsystem in embedded signal processing systems for data-intensive applications, through data representation in flash memories, data recording and retrieval in conventional optical data storage systems and the more recent holographic systems, to applications in medicine requiring massive image databases.

Flash memories and memory systems are key resources for the development of electronic products implementing converging technologies or exploiting solid-state memory disks. This book illustrates state-of-the-art technologies and research studies on Flash memories. Topics in modeling, design, programming, and materials for memories are covered along with real application examples.